VCVTPS2DQ

VCVTPS2DQ converts singles to signed doublewords, rounding as MXCSR.RC says, in VEX forms of 128 and 256 bits and EVEX forms up to 512. CVTPS2DQ explains the rounding, the integer indefinite 80000000H for NaNs and out-of-range values, and the difference from the truncating VCVTTPS2DQ, whose page also covers {sae}. What this form adds is the rounding mode in the instruction.

Floor and ceiling in one instruction#

The 512-bit register form takes {rn-sae}, {rd-sae}, {ru-sae} or {rz-sae}, so it converts with a fixed direction whatever MXCSR says: {rd-sae} is (int)floorf(x) for every element in range and {ru-sae} is the ceiling. In the cases recorded on Zen 5:

• {ru-sae} turned 1.5, 2.5 and -2.5 into 2, 3 and -2, and 10^-30 into 1;
• {rd-sae} turned -1 into -1 and the smallest normal single into 0, and, with DAZ set, the denormal -2^-127 into 0 rather than -1;
• {rn-sae} turned 2.5 into 2 and -2.5 into -2, ties to even.

These rounding operands also report nothing: with every exception unmasked (MXCSR 0 or 6000H), -2,147,483,904, the largest single and a signaling NaN each gave 80000000H, with no #XM and MXCSR unchanged. Without them, a signaling NaN raised #XM when invalid was unmasked.

What compilers emit#

The embedded rounding is there for intrinsics: _mm512_cvt_roundps_epi32(x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC) becomes vcvtps2dq zmm0, zmm0, {rd-sae} in our builds. Loops do not use it. At -O2 with -fno-math-errno, a loop of (int)floorf(a[i]) in Clang 23 rounds with VROUNDPS, immediate 9, and truncates with VCVTTPS2DQ (on zmm with VRNDSCALEPS for znver5); GCC 14 keeps it scalar. For (int)rintf(a[i]), Clang uses VCVTPS2DQ itself on ymm registers for -march=x86-64-v3 and x86-64-v4, and zmm for znver5, while GCC rounds with VROUNDPS (VRNDSCALEPS for x86-64-v4) and truncates. With x86-64-v4, Clang turns lrintf loops into VCVTPS2QQ, where GCC converts one element at a time.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = cvt_int(src2.f32[i], 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPS2DQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD

All 253 AVX instructions

More AVX10.1 instructions

• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS

All 686 AVX10.1 instructions