Instruction
VCVTPS2HF8
Converts packed single-precision values to E4M3 FP8, rounding to nearest even.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
VCVTPS2HF8 rounds each single to the 8-bit E4M3 format, which the mnemonics call HF8, to nearest even, and packs the bytes into the low end of an xmm register as VCVTPS2BF8 does for E5M2: 4, 8 or 16 singles give 4, 8 or 16 bytes, the rest of the register is cleared, and the write mask has one bit per result byte. It belongs to AVX10_V2_AUX, which the ACE specification defines: opcode 38h with the F3 prefix in EVEX map 5, W0. TDPHF8PS describes the format: a bias of 7, 448 as the largest value, and no infinity, only a NaN at 7Fh and FFh. VCVTPS2HF8S saturates, VCVTROPS2HF8 rounds to odd, VCVTPH2HF8 converts halves, and VCVTHF82PS converts back.
Both ends of the range
Above 448 the only encoding left is 7Fh, the NaN. A single up to 464, halfway to the 480 that 7Fh would otherwise hold, still rounds to 448 (7Eh): 464 itself is a tie, and 448’s fraction is the even one. Anything larger, an infinity and a NaN all give the NaN with the single’s sign; VCVTPS2HF8S gives 448 for all but the NaN.
At the bottom, results below 2^-6 are E4M3 denormals in steps of 2^-9, rounded to nearest even, and a single of 2^-10 or less gives a zero of its sign. A denormal single counts as a zero. Denormal results are not flushed, although XED marks the forms as flushing them, and MXCSR is neither read nor written: no flag, no exception. As examples, 1.0 gives 38h, and the single nearest 0.1 gives 1Dh, which is 0.1015625.
In our builds
Neither compiler has the instruction: Clang 23’s assembler and GNU as
2.44 reject the mnemonic, and Clang 23’s headers lack _mm512_cvtps_hf8
and the other intrinsics that ACE names. This site’s recorded cases
include none of VCVTPS2HF8.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VCVTPS2HF8 xmm {k}{z}, xmm
VCVTPS2HF8_XMMhf8_MASKmskw_XMMf32_AVX512 | EVEX.128.F3.MAP5.W0 38 /r | AVX10_V2_AUX + AVX10 |
VCVTPS2HF8 xmm {k}{z}, m128/m32bcst
VCVTPS2HF8_XMMhf8_MASKmskw_MEMf32_AVX512_VL128 | EVEX.128.F3.MAP5.W0 38 /r | AVX10_V2_AUX + AVX10 |
VCVTPS2HF8 xmm {k}{z}, ymm
VCVTPS2HF8_XMMhf8_MASKmskw_YMMf32_AVX512 | EVEX.256.F3.MAP5.W0 38 /r | AVX10_V2_AUX + AVX10 |
VCVTPS2HF8 xmm {k}{z}, m256/m32bcst
VCVTPS2HF8_XMMhf8_MASKmskw_MEMf32_AVX512_VL256 | EVEX.256.F3.MAP5.W0 38 /r | AVX10_V2_AUX + AVX10 |
VCVTPS2HF8 xmm {k}{z}, zmm
VCVTPS2HF8_XMMhf8_MASKmskw_ZMMf32_AVX512 | EVEX.512.F3.MAP5.W0 38 /r | AVX10_V2_AUX + AVX10 |
VCVTPS2HF8 xmm {k}{z}, m512/m32bcst
VCVTPS2HF8_XMMhf8_MASKmskw_MEMf32_AVX512_VL512 | EVEX.512.F3.MAP5.W0 38 /r | AVX10_V2_AUX + AVX10 |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Shown for the zmm form; the xmm and ymm forms work the same on 4 and 8 singles. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.
Result bytes 15 to 0: a15, unchanged (bit 14 of k1 is 0), a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 32):
if k1[i]:
xmm1.hf8[i] = to_hf8(src2.f32[i])
elif zeroing:
xmm1.hf8[i] = 0
# else: xmm1.hf8[i] keeps its value
for i in range(VL // 32, 16):
xmm1.b[i] = 0
# m32bcst: src2.f32[i] is the m32 for every i
# HF8: to nearest even, denormals kept, no flags; MXCSR unused
# xmm1 is zeroed from bit 128 upNot run on a processor: none of these processors has AVX10.2. The tests check its arithmetic against MPFR.
Operands
| Operand | Kind | Action |
|---|---|---|
VCVTPS2HF8 xmm {k}{z}, xmm/m128/m32bcst VCVTPS2HF8 xmm {k}{z}, ymm/m256/m32bcst VCVTPS2HF8 xmm {k}{z}, zmm/m512/m32bcst | ||
xmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcst | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
AVX512-E4
Attributes
What else XED records about the forms. How to read.
- All forms
- write masking
- Memory forms
- embedded broadcast (tuple Full); memory fault suppression
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX10_V2_AUX_128 | AVX10_V2_AUX + AVX10 | None in XED’s chip model, which lists these instructions only under its placeholder for future processors. |
AVX10_V2_AUX_256 | Same as AVX10_V2_AUX_128 | None in XED’s chip model, which lists these instructions only under its placeholder for future processors. |
AVX10_V2_AUX_512 | Same as AVX10_V2_AUX_128 | None in XED’s chip model, which lists these instructions only under its placeholder for future processors. |
More AVX10_V2_AUX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.