VCVTPS2IBS

VCVTPS2IBS converts each single to a signed byte, rounding as MXCSR.RC says, and saturates: values above 127 give 7Fh, values below -128 give 80h and a NaN gives 0. The byte stays in place, in the low byte of its 32-bit element, and the three bytes above it are cleared, so 16 singles give 16 bytes spread across a zmm register; VPMOVDB packs them, as every value is already in range. Out-of-range values, infinities and NaNs set IE, and an inexact result in range sets PE; with invalid unmasked, the instruction raises #XM instead. VCVTPS2DQ, by contrast, returns 80000000h for all of those.

It belongs to AVX10.2: opcode 69h with the 66 prefix in EVEX map 5, W0, with a write mask, a broadcast single, and {er} on the 512-bit register form. Four opcodes make the family: 69h rounds to signed bytes and 6Bh to unsigned ones (VCVTPS2IUBS), and 68h and 6Ah truncate (VCVTTPS2IBS, VCVTTPS2IUBS). Without a prefix the same opcodes convert halves (VCVTPH2IBS), and with F2 bfloat16 values (VCVTBF162IBS).

Where the range ends#

Whether a value is out of range depends on the rounding. To nearest even, 127.4 gives 127 with PE alone, but 127.5 rounds to 128 and so gives 7Fh with IE; -128.5 rounds to the even -128 and stays in range. Rounding up, anything above 127 is out of range, and rounding down, anything below -128. The specification’s descriptions of the signed conversions give the minimum as 2^(w-1), without its sign, where w is the width of the result; its helper functions return 80h, that is -128.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles _mm512_ipcvts_ps_epi8 to vcvtps2ibs zmm0, zmm0, and _mm512_ipcvts_roundps_epi8(x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC) to vcvtps2ibs zmm0, zmm0, {rd-sae}; _mm256_ and _mm_ forms exist. A loop that clamps floats to -128 and 127 and stores them as int8_t keeps VMAXPS, VMINPS, VCVTTPS2DQ and VPMOVDB. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = src2.f32[i]
        zmm1.d[i] = cvts_int(a, 8) & 0xFF
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPS2IBS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16

All 96 AVX10.2 instructions