VCVTPS2IUBS

VCVTPS2IUBS converts each single to an unsigned byte, rounding as MXCSR.RC or the {er} operand says: values above 255 give FFh, values below 0 give 0, and a NaN gives 0. As for the signed VCVTPS2IBS, whose page covers the in-place layout, the encoding and the rest of the family, each byte stays in the low byte of its doubleword with the three bytes above it cleared, and values out of range, infinities and NaNs set IE. Its opcode is 6Bh, two above VCVTPS2IBS’s 69h. VCVTPS2UDQ returns FFFFFFFFh for all of those instead, so a negative single there reads as the largest value.

Two ranges in the specification#

The instruction’s description puts the range after rounding, as for the signed form: to nearest even, 255.7 rounds to 256 and -0.7 to -1, both out of range. The specification’s helper function for this conversion checks a fixed range instead, -1 or less and 256 or more, whatever the rounding: by it those two values give FFh and 0 with PE, not IE. The helper for the half-precision VCVTPH2IUBS has a range for each rounding mode, below -1/2 or from 255.5 when rounding to nearest, as the description has it. The helper’s own comment is the text of the bfloat16 form, which rounds to nearest even and reports nothing.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles _mm512_ipcvts_ps_epu8 to vcvtps2iubs zmm0, zmm0. A loop that clamps floats to 0 and 255 and stores them as uint8_t keeps VMAXPS, VMINPS, VCVTTPS2DQ and VPMOVDB. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = src2.f32[i]
        zmm1.d[i] = cvts_uint(a, 8)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPS2IUBS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS

All 96 AVX10.2 instructions