VCVTPS2PD

VCVTPS2PD widens singles to doubles, exactly: four from an xmm register or 16 bytes into a ymm register with VEX, eight from a ymm register into a zmm one with EVEX. CVTPS2PD explains why the conversion cannot round, why each instruction reads only half a register’s worth of singles, and how GCC and Clang arrange the halves of an array. What the VEX and EVEX forms add:

• Masks per double. Each mask bit selects one result double, so a zmm destination takes eight bits. On Zen 5, vcvtps2pd zmm14{k5}, ymm8, {sae} with E1H in the low byte of K5 converted elements 0, 5, 6 and 7 and left the others as they were.
• A broadcast single. dword bcst widens one single into every element.
• {sae} without rounding. A widening conversion is always exact, so the EVEX register form takes only {sae}, which silences the two exceptions it can raise: invalid for a signaling NaN and denormal for a denormal input. In that case, with MXCSR 1E40H (invalid and denormal unmasked), the signaling NaN 7F812345H became a quiet NaN, with no fault and no flag.

What becomes of a NaN#

The single’s payload moves to the top of the double’s: Zen 5 widened 7FC12345H to 7FF82468A0000000H, the 23-bit fraction shifted up by 29 places, and the signaling 7F812345H to the same quiet value, setting IE where {sae} was absent. VCVTPD2PS narrows the other way and drops the low 29 bits.

Denormal inputs#

Every single denormal is a normal double. With DAZ clear, Zen 5 widened -2^-127 (80400000H) to the double -2^-127 and set the denormal flag; with DAZ set, the same input gave -0.

In our builds at -O2, Clang 23 widens straight from memory, to ymm registers for -march=x86-64-v3 and x86-64-v4 and to zmm for znver5; GCC 14 loads a whole vector and splits it, with VEXTRACTF128 for x86-64-v3 and VEXTRACTF32X8 on zmm registers for x86-64-v4.

In the optimization guide

What the optimization guide says about VCVTPS2PD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: The 256-bit forms that widen or insert data loaded from memory take two dependent micro-ops.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        zmm1.f64[i] = to_f64(src2.f32[i])
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

VCVTPS2PD zmm {k}{z}, ymm/m256/m32bcst, {sae}

AVX512-E3

VCVTPS2PD xmm {k}{z}, xmm/m64/m32bcst VCVTPS2PD ymm {k}{z}, xmm/m128/m32bcst

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Half); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPS2PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS

All 253 AVX instructions

More AVX10.1 instructions

• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD

All 686 AVX10.1 instructions