x86-64.net

Instruction

VCVTPS2PH

Converts packed singles to half precision, rounding as an immediate or MXCSR selects.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTPS2PH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTPS2PH m64, xmm, imm8 VCVTPS2PH_MEMq_XMMdq_IMMbVEX.128.66.0F3A.W0 1D /r ibF16C
VCVTPS2PH xmm, xmm, imm8 VCVTPS2PH_XMMq_XMMdq_IMMbVEX.128.66.0F3A.W0 1D /r ibF16C
VCVTPS2PH m128, ymm, imm8 VCVTPS2PH_MEMdq_YMMqq_IMMbVEX.256.66.0F3A.W0 1D /r ibF16C
VCVTPS2PH xmm, ymm, imm8 VCVTPS2PH_XMMdq_YMMqq_IMMbVEX.256.66.0F3A.W0 1D /r ibF16C
VCVTPS2PH ymm {k}{z}, zmm, imm8, {sae} VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512EVEX.512.66.0F3A.W0 1D /r ibAVX10.1 or AVX512F
VCVTPS2PH m256 {k}, zmm, imm8 VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512EVEX.512.66.0F3A.W0 1D /r ibAVX10.1 or AVX512F
VCVTPS2PH xmm {k}{z}, xmm, imm8 VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512EVEX.128.66.0F3A.W0 1D /r ibAVX10.1 or AVX512F + AVX512VL
VCVTPS2PH m64 {k}, xmm, imm8 VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512EVEX.128.66.0F3A.W0 1D /r ibAVX10.1 or AVX512F + AVX512VL
VCVTPS2PH xmm {k}{z}, ymm, imm8 VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512EVEX.256.66.0F3A.W0 1D /r ibAVX10.1 or AVX512F + AVX512VL
VCVTPS2PH m128 {k}, ymm, imm8 VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512EVEX.256.66.0F3A.W0 1D /r ibAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPS2PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtps_ph __m128i _mm_cvtps_ph(__m128 a, const int imm)

VCVTPS2PH xmm, xmm, imm8 VEX.128 -mf16c

_mm_mask_cvt_roundps_ph __m128i _mm_mask_cvt_roundps_ph(__m128i W, __mmask8 U, __m128 A, const int I)

VCVTPS2PH xmm {k}, xmm, imm8 EVEX.128 -mavx512vl

_mm_maskz_cvt_roundps_ph __m128i _mm_maskz_cvt_roundps_ph(__mmask8 U, __m128 A, const int I)

VCVTPS2PH xmm {k}{z}, xmm, imm8 EVEX.128 -mavx512vl

_mm256_cvtps_ph __m128i _mm256_cvtps_ph(__m256 a, const int imm)

VCVTPS2PH xmm, ymm, imm8 VEX.256 -mf16c

_mm256_mask_cvt_roundps_ph __m128i _mm256_mask_cvt_roundps_ph(__m128i W, __mmask8 U, __m256 A, const int I)

VCVTPS2PH xmm {k}, ymm, imm8 EVEX.256 -mavx512vl

_mm256_maskz_cvt_roundps_ph __m128i _mm256_maskz_cvt_roundps_ph(__mmask8 U, __m256 A, const int I)

VCVTPS2PH xmm {k}{z}, ymm, imm8 EVEX.256 -mavx512vl

_mm512_cvt_roundps_ph __m256i _mm512_cvt_roundps_ph(__m512 A, const int I)

VCVTPS2PH ymm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cvt_roundps_ph __m256i _mm512_mask_cvt_roundps_ph(__m256i U, __mmask16 W, __m512 A, const int I)

VCVTPS2PH ymm {k}, zmm, imm8 EVEX.512 -mavx512f

_mm512_maskz_cvt_roundps_ph __m256i _mm512_maskz_cvt_roundps_ph(__mmask16 W, __m512 A, const int I)

VCVTPS2PH ymm {k}{z}, zmm, imm8 EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
F16C

F16C
CPUID.01H:ECX[29] F16C

Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2

Note: XED gives Bulldozer F16C; GCC enables it from -march=bdver2 (Piledriver) on.

AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.