VCVTPS2PH

VCVTPS2PH narrows singles to half precision: four from an XMM register or eight from a YMM register, into the low half of an XMM register or straight to memory. It is the F16C partner of VCVTPH2PS, and unlike that one it rounds: a half has 11 significant bits and a largest finite value of 65504.

The immediate#

Its immediate chooses the rounding: with bit 2 clear, bits 1:0 give it (00 nearest, 01 down, 10 up, 11 toward zero); with bit 2 set, MXCSR.RC decides. Intel’s manual says that bits 7:3 are ignored and AMD’s says nothing of them; Zen 5 ignored them, converting with 08h as with 00h and with FCh as with 04h. GCC 14 and Clang 23 at -O2 with -mf16c use 4 for C’s conversion of a float to _Float16, so the program’s rounding mode applies; _cvtss_sh(x, 0) gets 0.

Out of range#

Both manuals say that MXCSR.FTZ has no effect: results below the smallest normal half become half denormals. Zen 5 agreed, rounding the single 00000001h up to the half 0001h with FTZ set, and setting UE, PE and DE. Rounding to nearest turns 65520 and more into infinity, with OE and PE set; rounding toward zero never goes past 65504. A NaN keeps the top bits of its payload: 7FC12345h became 7E09h. With an exception unmasked, the instruction raises #XM and writes nothing, which the cases recorded on Zen 5 show for a signaling NaN input.

In compiled code#

A loop narrowing an array of floats to _Float16 becomes the YMM form with a memory destination in Clang; GCC converts each element alone and stores it with VPEXTRW. Intel’s optimization manual found the instruction about four times faster than converting with integer instructions (Example 15-32). A double is not narrowed through a single, which could round twice: both compilers call the library’s __truncdfhf2 for it.

The EVEX forms (AVX-512F or AVX10.1) narrow sixteen singles and add a mask, with merging only when the destination is memory; VCVTPS2PHX of AVX512-FP16 adds broadcast and an embedded rounding mode. The instruction table of AMD’s Zen 5 guide gives the XMM form one macro-op with a latency of three cycles.

In the optimization guide

What the optimization guide says about VCVTPS2PH, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen and Zen+

• Vectors and floating point: Carry-less multiplication with PCLMULQDQ and the half-precision conversions VCVTPH2PS and VCVTPS2PH are microcoded, in AMD’s spreadsheet and in LLVM’s model.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f32[i]
        mem.f16[i] = to_f16(a, imm8)
    # else: mem.f16[i] is not written
# imm8[1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f32[i]
        ymm1.f16[i] = to_f16(a, imm8)
    elif zeroing:
        ymm1.f16[i] = 0
    # else: ymm1.f16[i] keeps its value
for i in range(VL // 32, 8):
    ymm1.w[i] = 0
# {sae}: no exception flags
# imm8[1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-11

EVEX forms

AVX512-E11

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPS2PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More F16C instructions

• VCVTPH2PS

More AVX10.1 instructions

• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH

All 686 AVX10.1 instructions