x86-64.net

Instruction

VCVTPS2PHX

Converts packed singles to half precision like VCVTPS2PH, but with a broadcast source and embedded rounding instead of an immediate.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTPS2PHX that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTPS2PHX xmm {k}{z}, xmm VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512EVEX.128.66.MAP5.W0 1D /rAVX10.1 or AVX512_FP16 + AVX512VL
VCVTPS2PHX xmm {k}{z}, m128/m32bcst VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128EVEX.128.66.MAP5.W0 1D /rAVX10.1 or AVX512_FP16 + AVX512VL
VCVTPS2PHX xmm {k}{z}, ymm VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512EVEX.256.66.MAP5.W0 1D /rAVX10.1 or AVX512_FP16 + AVX512VL
VCVTPS2PHX xmm {k}{z}, m256/m32bcst VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256EVEX.256.66.MAP5.W0 1D /rAVX10.1 or AVX512_FP16 + AVX512VL
VCVTPS2PHX ymm {k}{z}, zmm, {er} VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512EVEX.512.66.MAP5.W0 1D /rAVX10.1 or AVX512_FP16
VCVTPS2PHX ymm {k}{z}, m512/m32bcst VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512EVEX.512.66.MAP5.W0 1D /rAVX10.1 or AVX512_FP16

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPS2PHX, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtxps_ph __m128h _mm_cvtxps_ph(__m128 __A)

VCVTPS2PHX xmm, xmm EVEX.128 -mavx512fp16 -mavx512vl

_mm_mask_cvtxps_ph __m128h _mm_mask_cvtxps_ph(__m128h __W, __mmask8 __U, __m128 __A)

VCVTPS2PHX xmm {k}, xmm EVEX.128 -mavx512fp16 -mavx512vl

_mm_maskz_cvtxps_ph __m128h _mm_maskz_cvtxps_ph(__mmask8 __U, __m128 __A)

VCVTPS2PHX xmm {k}{z}, xmm EVEX.128 -mavx512fp16 -mavx512vl

_mm256_cvtxps_ph __m128h _mm256_cvtxps_ph(__m256 __A)

VCVTPS2PHX xmm, ymm EVEX.256 -mavx512fp16 -mavx512vl

_mm256_mask_cvtxps_ph __m128h _mm256_mask_cvtxps_ph(__m128h __W, __mmask8 __U, __m256 __A)

VCVTPS2PHX xmm {k}, ymm EVEX.256 -mavx512fp16 -mavx512vl

_mm256_maskz_cvtxps_ph __m128h _mm256_maskz_cvtxps_ph(__mmask8 __U, __m256 __A)

VCVTPS2PHX xmm {k}{z}, ymm EVEX.256 -mavx512fp16 -mavx512vl

_mm512_cvtx_roundps_ph __m256h _mm512_cvtx_roundps_ph(__m512 A, const int R)

VCVTPS2PHX ymm, zmm, {er} EVEX.512 -mavx512fp16

_mm512_cvtxps_ph __m256h _mm512_cvtxps_ph(__m512 __A)

VCVTPS2PHX ymm, zmm EVEX.512 -mavx512fp16

_mm512_mask_cvtx_roundps_ph __m256h _mm512_mask_cvtx_roundps_ph(__m256h W, __mmask16 U, __m512 A, const int R)

VCVTPS2PHX ymm {k}, zmm, {er} EVEX.512 -mavx512fp16

_mm512_mask_cvtxps_ph __m256h _mm512_mask_cvtxps_ph(__m256h __W, __mmask16 __U, __m512 __A)

VCVTPS2PHX ymm {k}, zmm EVEX.512 -mavx512fp16

_mm512_maskz_cvtx_roundps_ph __m256h _mm512_maskz_cvtx_roundps_ph(__mmask16 U, __m512 A, const int R)

VCVTPS2PHX ymm {k}{z}, zmm, {er} EVEX.512 -mavx512fp16

_mm512_maskz_cvtxps_ph __m256h _mm512_maskz_cvtxps_ph(__mmask16 __U, __m512 __A)

VCVTPS2PHX ymm {k}{z}, zmm EVEX.512 -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_FP16_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16 + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_FP16_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16 + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_FP16_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.