VCVTPS2PHX

VCVTPS2PHX narrows singles to half precision: four from an XMM register into the low 64 bits of an XMM register, eight from a YMM register, sixteen from a ZMM register into a YMM register, with the rest of the destination cleared. It converts as VCVTPS2PH does, rounding to the 11 significant bits of a half, but its encoding is that of the other AVX512-FP16 arithmetic, opcode 1Dh in EVEX map 5 with the 66 prefix.

Next to VCVTPS2PH#

• Rounding. There is no immediate: VCVTPS2PHX rounds by MXCSR.RC, or by {er} on the 512-bit register form, as VADDPH does. _mm512_cvtx_roundps_ph(x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC) becomes vcvtps2phx ymm0, zmm0, {rz-sae} in GCC 14 and Clang 23, where _mm512_cvtps_ph(x, _MM_FROUND_TO_ZERO) is VCVTPS2PH with immediate 3.
• Broadcast, but no store. The source can be one single broadcast from memory; the destination is always a register, so the masked store to memory of VCVTPS2PH has no counterpart.
• MXCSR. Intel’s entry says that DAZ applies to the single inputs, and that the half results are never flushed: a result below the smallest normal half is a denormal whatever FTZ says, as for VCVTPS2PH. DE is listed only when DAZ is clear.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, a loop h[i] = f[i] narrowing a float array to _Float16 becomes VCVTPS2PHX in both compilers, with the source in memory and a separate store: GCC joins two YMM results with VINSERTI64X4 for one ZMM store, Clang stores XMM results. With only F16C, Clang used VCVTPS2PH with a memory destination, as its page shows. A single float is narrowed with VCVTSS2SH, and VCVTPH2PSX is the way back. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTPS2PHX.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        ymm1.f16[i] = to_f16(src2.f32[i])
    elif zeroing:
        ymm1.f16[i] = 0
    # else: ymm1.f16[i] keeps its value
for i in range(VL // 32, 8):
    ymm1.w[i] = 0
# m32bcst: src2.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPS2PHX, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI

All 686 AVX10.1 instructions