VCVTPS2QQ

VCVTPS2QQ converts singles to signed quadwords, each to an element twice its width: 2 singles from the low half of an XMM register or from memory fill an XMM register, 4 a YMM register and 8 a ZMM one. It rounds as MXCSR.RC says or, in the 512-bit register form, as its {er} operand says. It came with AVX512DQ, and is the single-source form of VCVTPD2QQ, whose page covers the range and the integer indefinite, 8000000000000000h. Every single from -2^63 up to below 2^63 fits; VCVTTPS2QQ truncates instead, and VCVTPS2UQQ converts to unsigned quadwords.

Recorded on Zen 5#

• Infinity. {evex} vcvtps2qq xmm24, xmm3 turned -0.0 into 0 and +infinity into 8000000000000000h, and set IE.
• An override. Under {rz-sae}, 1.0, -1.0, -0.5, 1.5 and 2.5 gave 1, -1, 0, 1 and 2, without a flag.
• Sign extended. With MXCSR rounding down, -2^31, CF000000h, gave FFFFFFFF80000000h, its sign carried through the upper doubleword.
• Precision. A broadcast 0.5, truncated by MXCSR, gave 0 in the elements K1 selects and set PE.

In compiled code#

At -O2 with -march=x86-64-v4 -ffast-math, Clang 23 vectorizes s[i] = llrintf(f[i]) over a float and an int64_t array with VCVTPS2QQ on YMM registers, reading 4 singles at a time from memory; GCC 14 converts one at a time with VCVTSS2SI, and without -ffast-math both call llrintf. Both compile _mm512_cvtps_epi64 to vcvtps2qq zmm0, ymm0.

AMD’s Zen 5 latency spreadsheet gives the XMM form and the YMM form from memory one macro-op on pipe FP2 or FP3 and 3 cycles, the YMM form from a register two macro-ops and 4 cycles, and the ZMM form two macro-ops and 6 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = cvt_int(src2.f32[i], 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Half); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPS2QQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI

All 686 AVX10.1 instructions