VCVTPS2UDQ

VCVTPS2UDQ converts singles to unsigned doublewords, 4, 8 or 16 at a time, rounding as MXCSR.RC says or as an {er} rounding override on the 512-bit register form says. It is the rounding form of VCVTTPS2UDQ, whose page covers the unsigned range and its indefinite value, FFFFFFFFh, and the unsigned partner of VCVTPS2DQ. The range is 0 to 2^32 - 1 after rounding, so a negative value is out of range unless it rounds to 0. It came with AVX512F and takes a write mask and a 32-bit broadcast.

Recorded on Zen 5#

• 2^31 is valid. With RC rounding down, 2^31 gave 80000000h, the signed conversion’s indefinite value and here an ordinary result; -2.5 and the single just below -2^31 gave FFFFFFFFh and set IE.
• Rounding up. With RC rounding up, 1.0 gave 1, and -1.0, the largest single and the most negative one gave FFFFFFFFh.
• An override. vcvtps2udq zmm9{k4}, zmm9, {rn-sae}, with IE unmasked in MXCSR, gave FFFFFFFFh for 2^32, -2^32, 2^63 and a large value without a fault or a flag, and 7FFFFF80h for 2147483520.0.
• NaNs and denormals. From memory with DAZ set, a quiet NaN gave FFFFFFFFh and set IE, and two denormals gave 0.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile _mm512_cvtps_epu32 to VCVTPS2UDQ. Neither uses it for C: a loop of (uint32_t)rintf(f[i]) rounds first, with VRNDSCALEPS in GCC and VROUNDPS in Clang, and then truncates with VCVTTPS2UDQ.

AMD’s Zen 5 latency spreadsheet gives every width one macro-op on pipe FP2 or FP3 and 3 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = src2.f32[i]
        zmm1.d[i] = cvt_uint(a, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPS2UDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ

All 686 AVX10.1 instructions