VCVTPS2UQQ

VCVTPS2UQQ converts singles to unsigned quadwords, 2, 4 or 8 at a time into an XMM, YMM or ZMM register, rounding as MXCSR.RC says or, in the 512-bit register form, as its {er} operand says. It is the unsigned partner of VCVTPS2QQ, which came with it in AVX512DQ, and the quadword form of VCVTPS2UDQ, whose page covers the rounding cases. The range is 0 to 2^64 - 1 after rounding; a negative value that does not round to 0, a NaN or an infinity, or a value of 2^64 or more gives FFFFFFFFFFFFFFFFh and sets IE.

Recorded on Zen 5#

• NaNs and DAZ. With DAZ and rounding up, a negative signaling NaN gave FFFFFFFFFFFFFFFFh and set IE, while the smallest denormal gave 0: as a zero, it has nothing to round up.
• An override. vcvtps2uqq zmm7{k5}, ymm12, {rd-sae} gave 4 for 4.0, 3 for 3.0 and 0 for 0.1, and FFFFFFFFFFFFFFFFh for -2.5, which rounds down to -3, with IE unmasked and no fault.
• Large singles. 4EFFFFFFh, the largest single below 2^31, gave 7FFFFF80h, here and as a broadcast.
• A quiet NaN from memory, FFC00005h, also gave FFFFFFFFFFFFFFFFh with IE.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile _mm512_cvtps_epu64 to vcvtps2uqq zmm0, ymm0. Neither uses it for C: a loop of (uint64_t)rintf(f[i]) rounds with VRNDSCALEPS in GCC and VROUNDPS in Clang, then truncates with VCVTTPS2UQQ.

AMD’s Zen 5 latency spreadsheet gives the same rows as for VCVTPS2QQ: 3 cycles for the XMM form, 4 for YMM from a register and 6 for ZMM.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f32[i]
        zmm1.q[i] = cvt_uint(a, 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Half); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTPS2UQQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ

All 686 AVX10.1 instructions