x86-64.net

Instruction

VCVTQQ2PD

Converts packed signed quadwords to doubles.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTQQ2PD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTQQ2PD xmm {k}{z}, xmm VCVTQQ2PD_XMMf64_MASKmskw_XMMi64_AVX512EVEX.128.F3.0F.W1 E6 /rAVX10.1 or AVX512DQ + AVX512VL
VCVTQQ2PD xmm {k}{z}, m128/m64bcst VCVTQQ2PD_XMMf64_MASKmskw_MEMi64_AVX512EVEX.128.F3.0F.W1 E6 /rAVX10.1 or AVX512DQ + AVX512VL
VCVTQQ2PD ymm {k}{z}, ymm VCVTQQ2PD_YMMf64_MASKmskw_YMMi64_AVX512EVEX.256.F3.0F.W1 E6 /rAVX10.1 or AVX512DQ + AVX512VL
VCVTQQ2PD ymm {k}{z}, m256/m64bcst VCVTQQ2PD_YMMf64_MASKmskw_MEMi64_AVX512EVEX.256.F3.0F.W1 E6 /rAVX10.1 or AVX512DQ + AVX512VL
VCVTQQ2PD zmm {k}{z}, zmm, {er} VCVTQQ2PD_ZMMf64_MASKmskw_ZMMi64_AVX512EVEX.512.F3.0F.W1 E6 /rAVX10.1 or AVX512DQ
VCVTQQ2PD zmm {k}{z}, m512/m64bcst VCVTQQ2PD_ZMMf64_MASKmskw_MEMi64_AVX512EVEX.512.F3.0F.W1 E6 /rAVX10.1 or AVX512DQ

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTQQ2PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtepi64_pd __m128d _mm_cvtepi64_pd(__m128i __A)

VCVTQQ2PD xmm, xmm EVEX.128 -mavx512vl -mavx512dq

_mm_mask_cvtepi64_pd __m128d _mm_mask_cvtepi64_pd(__m128d __W, __mmask8 __U, __m128i __A)

VCVTQQ2PD xmm {k}, xmm EVEX.128 -mavx512vl -mavx512dq

_mm_maskz_cvtepi64_pd __m128d _mm_maskz_cvtepi64_pd(__mmask8 __U, __m128i __A)

VCVTQQ2PD xmm {k}{z}, xmm EVEX.128 -mavx512vl -mavx512dq

_mm256_cvtepi64_pd __m256d _mm256_cvtepi64_pd(__m256i __A)

VCVTQQ2PD ymm, ymm EVEX.256 -mavx512vl -mavx512dq

_mm256_mask_cvtepi64_pd __m256d _mm256_mask_cvtepi64_pd(__m256d __W, __mmask8 __U, __m256i __A)

VCVTQQ2PD ymm {k}, ymm EVEX.256 -mavx512vl -mavx512dq

_mm256_maskz_cvtepi64_pd __m256d _mm256_maskz_cvtepi64_pd(__mmask8 __U, __m256i __A)

VCVTQQ2PD ymm {k}{z}, ymm EVEX.256 -mavx512vl -mavx512dq

_mm512_cvt_roundepi64_pd __m512d _mm512_cvt_roundepi64_pd(__m512i A, const int R)

VCVTQQ2PD zmm, zmm, {er} EVEX.512 -mavx512dq

_mm512_cvtepi64_pd __m512d _mm512_cvtepi64_pd(__m512i __A)

VCVTQQ2PD zmm, zmm EVEX.512 -mavx512dq

_mm512_mask_cvt_roundepi64_pd __m512d _mm512_mask_cvt_roundepi64_pd(__m512d W, __mmask8 U, __m512i A, const int R)

VCVTQQ2PD zmm {k}, zmm, {er} EVEX.512 -mavx512dq

_mm512_mask_cvtepi64_pd __m512d _mm512_mask_cvtepi64_pd(__m512d __W, __mmask8 __U, __m512i __A)

VCVTQQ2PD zmm {k}, zmm EVEX.512 -mavx512dq

_mm512_maskz_cvt_roundepi64_pd __m512d _mm512_maskz_cvt_roundepi64_pd(__mmask8 U, __m512i A, const int R)

VCVTQQ2PD zmm {k}{z}, zmm, {er} EVEX.512 -mavx512dq

_mm512_maskz_cvtepi64_pd __m512d _mm512_maskz_cvtepi64_pd(__mmask8 __U, __m512i __A)

VCVTQQ2PD zmm {k}{z}, zmm EVEX.512 -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512DQ_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512DQ_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512DQ_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.