VCVTQQ2PH

VCVTQQ2PH converts signed quadwords to half precision, the vector form of C’s conversion from long to _Float16. The result is a quarter as wide as the source: 8 quadwords of a ZMM register become 8 halves filling an XMM register, 4 from a YMM register fill its low 64 bits and 2 from an XMM register its low 32 bits, with everything above cleared. The opcode is 5Bh without a prefix in EVEX map 5 with W1, which tells it apart from VCVTDQ2PH (W0), as W does for VCVTQQ2PS and CVTDQ2PS in the 0F map. VCVTUQQ2PH converts unsigned quadwords.

Sixty-four bits into sixteen#

A half is exact for integers up to 2048 and has no finite value past 65504, so nearly all of the quadword range overflows: in round to nearest, from 65520 up the result is infinity, and toward zero it is 65504; Intel’s entry lists overflow and precision. The rounding mode comes from MXCSR.RC, or from {er} on the 512-bit register form, and a quadword broadcast from memory is allowed. The VCVTDQ2PH page works through the rounding near the top of the range.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, Clang 23 converts an int64_t array into a _Float16 array with VCVTQQ2PH from YMM loads to XMM results, joining four of them with VINSERTF128 and VUNPCKLPD for a 32-byte store. GCC 14 does not use it, at -O2 or -O3: it converts each element with VCVTSI2SH straight from memory and stores the half with VMOVW. Without AVX512-FP16, at -march=x86-64-v3, Clang converts each element to a single with VCVTSI2SS and narrows it with VCVTPS2PH, the same result, since every integer a half can hold is exact as a single and the rest overflow either way; GCC loads each quadword with the x87 FILD and calls the library’s __truncxfhf2. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTQQ2PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        xmm1.f16[i] = to_f16(src2.sq[i])
    elif zeroing:
        xmm1.f16[i] = 0
    # else: xmm1.f16[i] keeps its value
for i in range(VL // 64, 8):
    xmm1.w[i] = 0
# m64bcst: src2.q[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTQQ2PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ

All 686 AVX10.1 instructions