VCVTQQ2PS

VCVTQQ2PS converts signed quadwords to singles, the vector form of C’s conversion from long to float. The result is half as wide as the source: 8 quadwords of a ZMM register become 8 singles in a YMM register, 4 from a YMM register fill an XMM register, and 2 from an XMM register fill its low 64 bits; everything above is cleared. It came with AVX512DQ, as VCVTQQ2PD did, whose page covers the conversion to doubles; VCVTUQQ2PS converts unsigned quadwords, and CVTDQ2PS doublewords.

Recorded on Zen 5#

• 24 bits of significand. Rounding down, 2^24 + 1 became 2^24 and set PE, while -1 and -2^63 converted exactly.
• Near 2^63. With {rz-sae} on the 512-bit register form, 2^63 - 1024 and 2^63 - 513 both became 2^63 - 2^39, the largest single below 2^63, -2^63 + 1 became -(2^63 - 2^39), and 2^31 - 64 became 2^31 - 128. MXCSR had PE unmasked, yet nothing faulted and PE stayed clear: the {sae} part suppresses the flags.
• Nothing selected. vcvtqq2ps xmm5{k1}, ymmword ptr [mem], with the low four bits of K1 clear, kept the four singles of XMM5 and cleared the register above bit 127.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile f[i] = (float)q[i] over int64_t and float arrays to VCVTQQ2PS with the source in memory. GCC converts two ZMM loads to YMM halves and joins them with VINSERTF32X8 for one ZMM store; Clang converts YMM loads to XMM registers and stores those. For a loop of unknown length Clang still uses VCVTQQ2PS, while GCC converts one element at a time with VCVTSI2SS. With -march=x86-64-v3, which has no AVX512DQ, both convert one element at a time, Clang gathering four results with VINSERTPS. _mm512_cvt_roundepi64_ps with _MM_FROUND_TO_ZERO is the {rz-sae} form.

AMD’s Zen 5 latency spreadsheet gives VCVTQQ2PS one macro-op and 3 cycles from an XMM source, and two macro-ops with 6 cycles from a YMM source and 7 from a ZMM source.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        ymm1.f32[i] = to_f32(src2.sq[i])
    elif zeroing:
        ymm1.f32[i] = 0
    # else: ymm1.f32[i] keeps its value
for i in range(VL // 64, 4):
    ymm1.d[i] = 0
# m64bcst: src2.q[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTQQ2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ

All 686 AVX10.1 instructions