x86-64.net

Instruction

VCVTROPS2HF8

Converts packed single-precision values to E4M3 FP8, rounding to odd, which avoids double-rounding errors when the result is narrowed again.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTROPS2HF8 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTROPS2HF8 xmm {k}{z}, xmm VCVTROPS2HF8_XMMhf8_MASKmskw_XMMf32_AVX512EVEX.128.66.MAP5.W0 38 /rAVX10_V2_AUX + AVX10
VCVTROPS2HF8 xmm {k}{z}, m128/m32bcst VCVTROPS2HF8_XMMhf8_MASKmskw_MEMf32_AVX512_VL128EVEX.128.66.MAP5.W0 38 /rAVX10_V2_AUX + AVX10
VCVTROPS2HF8 xmm {k}{z}, ymm VCVTROPS2HF8_XMMhf8_MASKmskw_YMMf32_AVX512EVEX.256.66.MAP5.W0 38 /rAVX10_V2_AUX + AVX10
VCVTROPS2HF8 xmm {k}{z}, m256/m32bcst VCVTROPS2HF8_XMMhf8_MASKmskw_MEMf32_AVX512_VL256EVEX.256.66.MAP5.W0 38 /rAVX10_V2_AUX + AVX10
VCVTROPS2HF8 xmm {k}{z}, zmm VCVTROPS2HF8_XMMhf8_MASKmskw_ZMMf32_AVX512EVEX.512.66.MAP5.W0 38 /rAVX10_V2_AUX + AVX10
VCVTROPS2HF8 xmm {k}{z}, m512/m32bcst VCVTROPS2HF8_XMMhf8_MASKmskw_MEMf32_AVX512_VL512EVEX.512.66.MAP5.W0 38 /rAVX10_V2_AUX + AVX10

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX10_V2_AUX_128

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None yet: XED lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_256

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None yet: XED lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX_512

AVX10_V2_AUX + AVX10
CPUID.(EAX=24H,ECX=1):ECX[3] AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

None yet: XED lists these instructions only under its placeholder for future processors.

More AVX10_V2_AUX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.