VCVTSD2SH

VCVTSD2SH converts the low double of its last operand, a register or eight bytes of memory, to a half in the low 16 bits of the destination, copying bits 127:16 from the middle operand and clearing bits 128 and up. It is the conversion of C’s (_Float16) on a double, the scalar form of VCVTPD2PH, and the companion for doubles of VCVTSS2SH. The opcode is 5Ah with the F2 prefix in EVEX map 5 with W1, where VCVTSD2SS has F2 5Ah in the 0F map.

Rounding and flags#

The result is rounded by MXCSR.RC or, for a register source, by an {er} mode in the instruction, which also suppresses every exception; Intel’s description mentions only MXCSR, though the opcode table and the operation take the embedded mode. All five exceptions can be reported: invalid for a signaling NaN, denormal for a denormal double unless DAZ is set, overflow past 65504, underflow for an inexact result below 2^-14, and precision. A write mask applies to the low element.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile return x; from double to _Float16 to vcvtsd2sh xmm0, xmm0, xmm0, one rounding; (_Float16)(float)x stays two, VCVTSD2SS and then VCVTSS2SH, as written. In a loop that narrows an array, GCC 14.2.0 converts one element at a time with VCVTSD2SH, reading the double straight from memory, when the count is known only at run time or leaves a remainder, as 1,001 does; for a constant count that fills whole vectors, such as 1,024, it goes through singles, with VCVTPD2PS and then VCVTPS2PHX, which rounds twice. Global arrays and pointer parameters behave alike. Clang 23.1.2 uses VCVTPD2PH for every count and VCVTSD2SH only for the elements left over. Without AVX512-FP16, both call the library’s __truncdfhf2, as VCVTPS2PH’s page notes. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTSD2SH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f16[0] = to_f16(src3.f64[0])
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSD2SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ

All 686 AVX10.1 instructions