VCVTSD2SI

VCVTSD2SI is the VEX and EVEX form of CVTSD2SI: the low double of an XMM register or of eight bytes of memory, converted to a signed 32-bit or 64-bit integer in a general-purpose register and rounded as MXCSR.RC says. CVTSD2SI’s page covers the range, the integer indefinite and the C functions that reach it, and VCVTTSD2SI is the truncating twin. With a general-purpose destination there is nothing above it to zero, so the VEX form, which needs AVX, only asks for VEX.vvvv at 1111b. The EVEX form, with AVX-512F or AVX10.1, adds a rounding mode of its own, {rn-sae} to {rz-sae}, which replaces MXCSR.RC and suppresses exceptions, but only with a register source. Zen 5’s recorded cases:

• {evex} vcvtsd2si rax, xmm17, {rd-sae}, under MXCSR 6600H, where the precision and invalid exceptions are unmasked, converted 2.5 to 2 with no #XM and MXCSR unchanged.
• {evex} vcvtsd2si esi, qword ptr [mem], a memory form that takes its rounding from MXCSR, here FFC0H (toward zero), converted 2,147,483,647.5 to 7FFFFFFFh and set PE.
• vcvtsd2si r9d, qword ptr [mem] gave the integer indefinite, 80000000h, for the signaling NaN 7FF0000000012345H, set IE and cleared bits 63:32 of R9.

From lrint to VCVTPD2QQ#

In our builds at -O2 with -fno-math-errno, lrint(x) is vcvtsd2si rax, xmm0 in GCC 14 and Clang 23 at -march=x86-64-v3 and x86-64-v4, and (int)rint(x) is vcvtsd2si eax, xmm0 in Clang, where GCC rounds first, with VROUNDSD at -v3 or VRNDSCALESD at -v4, and truncates with VCVTTSD2SI. Over a global array of doubles, lrint stays one VCVTSD2SI per element from memory at -v3, Clang packing the results into vectors with VMOVQ and VPUNPCKLQDQ before storing them; at -v4 both use the packed VCVTPD2QQ. _mm_cvt_roundsd_si32(v, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC) gives vcvtsd2si eax, xmm0, {rd-sae}.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows two macro-ops on pipes FP2 or FP3 and FP4 or FP5, two per cycle; only the EVEX row gives a latency, 4 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f64[0]
dest.write(cvt_int(a, dest.bits))  # r32: bits 63:32 cleared
# {er}: the form's rounding, not MXCSR.RC, and no flags

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSD2SI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD

All 253 AVX instructions

More AVX10.1 instructions

• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ

All 686 AVX10.1 instructions