VCVTSD2SS

VCVTSD2SS is the VEX and EVEX form of CVTSD2SS, whose page covers what narrowing a double does: rounding as MXCSR.RC says, overflow, underflow and the NaN payload, with cases recorded on Zen 5 for this VEX form. What the newer encodings add is the first source: the single goes into bits 31:0, bits 127:32 come from the first source, and the register is cleared above bit 127. VEX needs AVX. The EVEX form, with AVX-512F or AVX10.1, adds a write mask on the low single and, for a register source, a rounding mode of its own, {rn-sae}, {rd-sae}, {ru-sae} or {rz-sae}, which replaces MXCSR.RC for this one instruction and reports no exception.

One register in two roles#

In the recorded vcvtsd2ss xmm7, xmm11, xmm7, XMM7 was both the double to narrow and the destination. Its low single became 7FC00000h, the quiet NaN that CVTSD2SS’s page shows for the signaling NaN 7FF0000000012345h, IE was set, and singles 1 to 3 came from XMM11: nothing of the old XMM7 above bit 31 survived.

In compiled code#

In our builds at -O2 with -march=x86-64-v3 or -v4, (float)x of a double argument is vcvtsd2ss xmm0, xmm0, xmm0. A double read from a global array goes the two ways shown for VCVTSS2SD: GCC 14 zeroes XMM0 with VXORPS and converts from memory, Clang 23 loads with VMOVSD and converts register to register. Summing a double array into a float, GCC narrows four doubles at a time with VCVTPD2PS (eight at -v4) and adds the singles in order, while Clang stays scalar, narrowing each loaded register into itself. _mm_cvt_roundsd_ss(a, b, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC) gives vcvtsd2ss xmm0, xmm0, xmm1, {rz-sae} in both.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike one macro-op with a latency of 3 cycles on pipes FP2 and FP3, the figures of CVTSD2SS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    xmm1.f32[0] = to_f32(src3.f64[0])
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSD2SS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS

All 253 AVX instructions

More AVX10.1 instructions

• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ

All 686 AVX10.1 instructions