VCVTSH2SD

VCVTSH2SD converts the low half of its last operand, a register or two bytes of memory, to a double in the low 64 bits of the destination, copying bits 127:64 from the middle operand and clearing bits 128 and up. Every half is exactly a double, so nothing is rounded: the instruction takes {sae} but no rounding mode. It is the scalar form of VCVTPH2PD, whose page covers the exceptions it shares, invalid and denormal, and the opcode is 5Ah with the F3 prefix in EVEX map 5, where VCVTSS2SD has F3 5Ah in the 0F map.

A denormal half#

The smallest normal half is 2^-14; below it the halves are denormal, down to 2^-24, and all of them become normal doubles. Intel’s entry lists the denormal exception for that case, while for the F16C conversion VCVTPH2PS it states that denormal halves raise none, so a program that unmasks DE can see this conversion fault where the older one would not. A signaling NaN is made quiet and sets IE. A write mask applies to the low element.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile return x; from _Float16 to double to vcvtsh2sd xmm0, xmm0, xmm0, and a sum of a _Float16 and a double to VCVTSH2SD and then VADDSD. In a loop that widens an array, GCC converts one element at a time with it, reading the half straight from memory, when the count is known only at run time or leaves a remainder, as 1,001 does; for a constant count that fills whole vectors, such as 1,024, it goes through singles instead, with VCVTPH2PSX and VCVTPS2PD, which is exact. Global arrays and pointer parameters behave alike. Clang uses VCVTPH2PD for every count and VCVTSH2SD only for the elements left over. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTSH2SD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f64[0] = to_f64(src3.f16[0])
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {sae}: no exception flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSH2SD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTPH2PSX
• VCVTPH2QQ
• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W

All 686 AVX10.1 instructions