Instruction
VCVTSH2SD
Converts the low half-precision value of the second source to double, which is exact; the other elements come from the first source.
- Extensions
- Forms
- 2 (2 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VCVTSH2SD xmm {k}{z}, xmm, xmm, {sae}
VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 | EVEX.LIG.F3.MAP5.W0 5A /r | AVX10.1 or AVX512_FP16 |
VCVTSH2SD xmm {k}{z}, xmm, m16
VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512 | EVEX.LIG.F3.MAP5.W0 5A /r | AVX10.1 or AVX512_FP16 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VCVTSH2SD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cvt_roundsh_sd
__m128d _mm_cvt_roundsh_sd(__m128d A, __m128h B, const int R) |
|
_mm_cvtsh_sd
__m128d _mm_cvtsh_sd(__m128d __A, __m128h __B) |
|
_mm_mask_cvt_roundsh_sd
__m128d _mm_mask_cvt_roundsh_sd(__m128d W, __mmask8 U, __m128d A, __m128h B, const int R) |
|
_mm_mask_cvtsh_sd
__m128d _mm_mask_cvtsh_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128h __B) |
|
_mm_maskz_cvt_roundsh_sd
__m128d _mm_maskz_cvt_roundsh_sd(__mmask8 U, __m128d A, __m128h B, const int R) |
|
_mm_maskz_cvtsh_sd
__m128d _mm_maskz_cvtsh_sd(__mmask8 __U, __m128d __A, __m128h __B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_FP16_SCALAR | AVX10.1 or AVX512_FP16 | Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
- VCVTPH2PSX
- VCVTPH2QQ
- VCVTPH2UDQ
- VCVTPH2UQQ
- VCVTPH2UW
- VCVTPH2W
- VCVTPS2DQ
- VCVTPS2PD
- VCVTPS2PH
- VCVTPS2PHX
- VCVTPS2QQ
- VCVTPS2UDQ
- VCVTPS2UQQ
- VCVTQQ2PD
- VCVTQQ2PH
- VCVTQQ2PS
- VCVTSD2SH
- VCVTSD2SI
- VCVTSD2SS
- VCVTSD2USI
- VCVTSH2SI
- VCVTSH2SS
- VCVTSH2USI
- VCVTSI2SD
- VCVTSI2SH
- VCVTSI2SS
- VCVTSS2SD
- VCVTSS2SH
- VCVTSS2SI
- VCVTSS2USI
- VCVTTPD2DQ
- VCVTTPD2QQ
- VCVTTPD2UDQ
- VCVTTPD2UQQ
- VCVTTPH2DQ
- VCVTTPH2QQ
- VCVTTPH2UDQ
- VCVTTPH2UQQ
- VCVTTPH2UW
- VCVTTPH2W
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.