VCVTSH2SI instruction (AVX10.1)

VCVTSH2SI converts the low half of an XMM register or of two bytes of memory to a signed integer in a general-purpose register, 32 bits or, with EVEX.W1 in 64-bit mode, 64 bits, rounding by MXCSR.RC or by an {er} mode on the register form. It is the half-precision form of VCVTSS2SI, with its opcode, 2Dh with F3, in EVEX map 5; VCVTTSH2SI truncates instead, and the packed forms are VCVTPH2DQ and VCVTPH2QQ.

Range

Every finite half lies within 65504 of zero, so both destination sizes hold any of them after rounding, and the indefinite value, 80000000h or 8000000000000000h with IE, comes only from a NaN or an infinity. A dropped fraction sets PE: 2.5 gives 2 and 3.5 gives 4 in round to nearest even.

In our builds

At -O2 with -march=x86-64-v4 -mavx512fp16, _mm_cvtsh_i32 gives vcvtsh2si eax, xmm0 in GCC 14 and Clang 23, and _mm_cvt_roundsh_i64 with _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC gives vcvtsh2si rax, xmm0, {ru-sae}. From C, GCC’s __builtin_lrintf16 compiles to it, reading the half straight from memory in a loop, but lrintf on a _Float16 widens first in both compilers: VCVTSH2SS and then VCVTSS2SI, the same result since the single is exact. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTSH2SI.

Forms

Every encoding of VCVTSH2SI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VCVTSH2SI r32, xmm, {er}` VCVTSH2SI_GPR32i32_XMMf16_AVX512	`EVEX.LIG.F3.MAP5.W0 2D /r`	AVX10.1 or AVX512_FP16
`VCVTSH2SI r32, m16` VCVTSH2SI_GPR32i32_MEMf16_AVX512	`EVEX.LIG.F3.MAP5.W0 2D /r`	AVX10.1 or AVX512_FP16
`VCVTSH2SI r64, xmm, {er}` 64-bit mode only VCVTSH2SI_GPR64i64_XMMf16_AVX512	`EVEX.LIG.F3.MAP5.W1 2D /r`	AVX10.1 or AVX512_FP16
`VCVTSH2SI r64, m16` 64-bit mode only VCVTSH2SI_GPR64i64_MEMf16_AVX512	`EVEX.LIG.F3.MAP5.W1 2D /r`	AVX10.1 or AVX512_FP16

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`r32, xmm, {er}` `r64, xmm, {er}`	`r32, m16` `r64, m16`
Sapphire Rapids	8 / 1p015	13 / 1p01

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low half of xmm2 is converted, and the integer goes to r32.

r32 receives the conversion of half 0 of xmm2: r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f16[0]
dest.write(cvt_int(a, dest.bits))  # r32: bits 63:32 cleared
# {er}: the form's rounding, not MXCSR.RC, and no flags

Not run on a processor: none of these processors has AVX512-FP16.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VCVTSH2SI r32, xmm/m16, {er}` `VCVTSH2SI r64, xmm/m16, {er}` 64-bit mode only
`r32/64`	explicit	write
`xmm/m16`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSH2SI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvt_roundsh_i32` `int _mm_cvt_roundsh_i32(__m128h A, const int R)`	`VCVTSH2SI r32, xmm, {er}` EVEX.LIG -mavx512fp16
`_mm_cvt_roundsh_i64` `long long _mm_cvt_roundsh_i64(__m128h A, const int R)`	`VCVTSH2SI r64, xmm, {er}` EVEX.LIG -mavx512fp16
`_mm_cvtsh_i32` `int _mm_cvtsh_i32(__m128h __A)`	`VCVTSH2SI r32, xmm` EVEX.LIG -mavx512fp16
`_mm_cvtsh_i64` `long long _mm_cvtsh_i64(__m128h __A)`	`VCVTSH2SI r64, xmm` EVEX.LIG -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512_FP16_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

AVX512_FP16_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Range#

In our builds#