VCVTSH2SS

VCVTSH2SS converts the low half of its last operand, a register or two bytes of memory, to a single in the low 32 bits of the destination, copying bits 127:32 from the middle operand and clearing bits 128 and up. Every half is exactly a single, so nothing is rounded; a signaling NaN is made quiet and sets IE, and Intel’s entry also lists the denormal exception. It is the scalar form of VCVTPH2PSX, takes a write mask on the low element and {sae}, and is the conversion of C’s (float) on a _Float16. VADDPH covers AVX512-FP16 and the format.

Encoding#

The opcode is 13h in EVEX map 6 with no prefix: the same byte as VCVTPH2PSX, which has the 66 prefix, as in the old maps CVTPS2PD and CVTSS2SD share 5Ah. Before AVX512-FP16, F16C had no scalar form, and a single half went through the packed VCVTPH2PS after the rest of the register was cleared or the word inserted. Intel’s optimization manual notes that a denormal half becomes a normal single (Section 18.5.7).

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile return x; from _Float16 to float to vcvtsh2ss xmm0, xmm0, xmm0, which keeps the result in the same register; _mm_cvtsh_ss gives it with two sources. Where a C library function has no FP16 version, both convert around the call: logbf and ldexpf on a _Float16 are VCVTSH2SS, the call, and VCVTSS2SH back, and GCC reads the half straight from memory in a loop. A minimum widened to float is VMINSH and then VCVTSH2SS. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTSH2SS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f32[0] = to_f32(src3.f16[0])
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {sae}: no exception flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSH2SS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTPH2UDQ
• VCVTPH2UQQ
• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ

All 686 AVX10.1 instructions