VCVTSI2SD

VCVTSI2SD converts a signed 32-bit or 64-bit integer, from a general-purpose register or memory, to a double in bits 63:0, with bits 127:64 from the first source and the register cleared above bit 127. CVTSI2SD covers the conversion, the wait on the merged register that the VEX form’s separate source exists to avoid, and the registers GCC 14 and Clang 23 name there: one zeroed before a loop, or XMM15. The VEX form needs AVX; the EVEX form, with AVX-512F or AVX10.1, has no write mask and adds a rounding mode only to the 64-bit register form. Every 32-bit integer has an exact double, and Intel’s entry says a rounding operand on the 32-bit EVEX form is ignored.

Recorded on Zen 5#

• {evex} vcvtsi2sd xmm24, xmm3, r14, {rz-sae} turned R14 = 8000000000000001h, -(2^63 - 1), into -(2^63 - 1024), C3DFFFFFFFFFFFFFh. MXCSR was 6600h, with the precision exception unmasked, and nothing was raised or flagged.
• The EVEX 64-bit memory form read 8008000000000000h, bytes that as a double would be a negative denormal, with DAZ set (FFC0h). As an integer it is -9,221,120,237,041,090,560, which converted exactly to C3DFFE0000000000h; DAZ applies to floating-point inputs only.
• vcvtsi2sd xmm7, xmm11, r9d read only R9D, 80000001h, and gave -2,147,483,647.0, whatever the upper half of R9 held.

In compiled code#

In our builds at -O2, (double)x of an int or long is the VEX form at -march=x86-64-v3 and still at -v4: GCC with a VXORPS of the destination first, Clang with XMM15 as the first source. At -v4 the other conversions change: an array of long becomes VCVTQQ2PD, eight or four at a time, and an unsigned int goes straight to VCVTUSI2SD, where -v3 zero-extends it and uses the 64-bit VCVTSI2SD. _mm_cvt_roundi64_sd(a, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC) gives vcvtsi2sd xmm0, xmm0, rdi, {rz-sae} in both.

AMD’s latency spreadsheet for Zen 5 lists the VEX and EVEX rows alike: two macro-ops from a register and one from memory, a latency of 3 cycles, the figures of VCVTSI2SS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f64[0] = to_f64(signed(src3))
xmm1.q[1] = xmm2.q[1]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

VCVTSI2SD xmm, xmm, r/m32

AVX512-E10NF

VCVTSI2SD xmm, xmm, r/m64, {er} 64-bit mode only

AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

VCVTSI2SD xmm, xmm, r/m32 VCVTSI2SD xmm, xmm, r/m64 64-bit mode only VCVTSI2SD xmm, xmm, r/m64, {er} 64-bit mode only

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSI2SD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128

All 253 AVX instructions

More AVX10.1 instructions

• VCVTPH2UW
• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ

All 686 AVX10.1 instructions