Instruction
VCVTSI2SH
Converts a signed 32- or 64-bit integer to half precision in the low element; the other elements come from the first source.
- Extensions
- Forms
- 4 (4 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VCVTSI2SH xmm, xmm, r32, {er}
VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 | EVEX.LIG.F3.MAP5.W0 2A /r | AVX10.1 or AVX512_FP16 |
VCVTSI2SH xmm, xmm, m32
VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 | EVEX.LIG.F3.MAP5.W0 2A /r | AVX10.1 or AVX512_FP16 |
VCVTSI2SH xmm, xmm, r64, {er} 64-bit mode only
VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 | EVEX.LIG.F3.MAP5.W1 2A /r | AVX10.1 or AVX512_FP16 |
VCVTSI2SH xmm, xmm, m64 64-bit mode only
VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 | EVEX.LIG.F3.MAP5.W1 2A /r | AVX10.1 or AVX512_FP16 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VCVTSI2SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cvt_roundi32_sh
__m128h _mm_cvt_roundi32_sh(__m128h A, int B, const int R) |
|
_mm_cvt_roundi64_sh
__m128h _mm_cvt_roundi64_sh(__m128h A, long long B, const int R) |
|
_mm_cvti32_sh
__m128h _mm_cvti32_sh(__m128h __A, int __B) |
|
_mm_cvti64_sh
__m128h _mm_cvti64_sh(__m128h __A, long long __B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_FP16_SCALAR | AVX10.1 or AVX512_FP16 | Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
- VCVTPH2W
- VCVTPS2DQ
- VCVTPS2PD
- VCVTPS2PH
- VCVTPS2PHX
- VCVTPS2QQ
- VCVTPS2UDQ
- VCVTPS2UQQ
- VCVTQQ2PD
- VCVTQQ2PH
- VCVTQQ2PS
- VCVTSD2SH
- VCVTSD2SI
- VCVTSD2SS
- VCVTSD2USI
- VCVTSH2SD
- VCVTSH2SI
- VCVTSH2SS
- VCVTSH2USI
- VCVTSI2SD
- VCVTSI2SS
- VCVTSS2SD
- VCVTSS2SH
- VCVTSS2SI
- VCVTSS2USI
- VCVTTPD2DQ
- VCVTTPD2QQ
- VCVTTPD2UDQ
- VCVTTPD2UQQ
- VCVTTPH2DQ
- VCVTTPH2QQ
- VCVTTPH2UDQ
- VCVTTPH2UQQ
- VCVTTPH2UW
- VCVTTPH2W
- VCVTTPS2DQ
- VCVTTPS2QQ
- VCVTTPS2UDQ
- VCVTTPS2UQQ
- VCVTTSD2SI
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.