VCVTSI2SH

VCVTSI2SH converts a signed integer from a general-purpose register or memory, 32 bits or, with EVEX.W1 in 64-bit mode, 64 bits, to a half in the low 16 bits of the destination, copying bits 127:16 from the middle operand and clearing bits 128 and up. It is the conversion of C’s (_Float16) on an int or a long, and the scalar form of VCVTDQ2PH and VCVTQQ2PH. The opcode is 2Ah with the F3 prefix in EVEX map 5, where VCVTSI2SS has F3 2Ah in the 0F map; outside 64-bit mode W is ignored.

Overflow, unlike VCVTSI2SS#

A single holds any 64-bit integer’s magnitude, so VCVTSI2SS lists only the precision exception; a half stops at 65504, and Intel’s entry for VCVTSI2SH adds overflow. In round to nearest every integer from 65520 up becomes infinity with OE and PE, toward zero it becomes 65504, and from 2049 up in magnitude an integer may be rounded. The rounding mode is MXCSR.RC or an {er} mode in the instruction, for a register source; there is no write mask.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, return x; from int to _Float16 is vcvtsi2sh xmm0, xmm0, edi in GCC 14 and vcvtsi2sh xmm0, xmm31, edi in Clang 23, which takes the untouched bits from XMM31, a register nothing else in the function writes, as it names XMM15 for the VEX conversions that CVTSI2SD’s page describes; GCC names the destination itself, an input the conversion has to wait for. For a short or signed char argument, GCC sign-extends it with MOVSX first, while Clang relies on the caller having done so; Clang also uses VCVTSI2SH for an unsigned short, which as a 32-bit value is never negative. _mm_cvt_roundi32_sh(a, b, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC) becomes vcvtsi2sh xmm0, xmm0, {rz-sae}, edi. Without AVX512-FP16, GCC converts an int to a double and calls __truncdfhf2, and Clang uses VCVTSI2SS and VCVTPS2PH. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTSI2SH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f16[0] = to_f16(signed(src3))
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSI2SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTPH2W
• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI

All 686 AVX10.1 instructions