VCVTSI2SS

VCVTSI2SS converts a signed 32-bit or 64-bit integer, from a general-purpose register or memory, to a single in bits 31:0, with bits 127:32 from the first source and the register cleared above bit 127. CVTSI2SS covers the rounding above 2^24 and the unsigned conversions, and CVTSI2SD the wait on the merged register and how GCC 14 and Clang 23 choose its first source. The VEX form needs AVX. The EVEX form, with AVX-512F or AVX10.1, has no write mask; what it adds is a rounding mode for a register source, at both sizes, since even a 32-bit integer may not fit a single.

Rounding given in the instruction#

{rn-sae}, {rd-sae}, {ru-sae} or {rz-sae} replaces MXCSR.RC and reports no exception. The cases recorded on Zen 5 ran under MXCSR 6600h, which asks for rounding toward zero and leaves the precision exception unmasked:

• {evex} vcvtsi2ss xmm1, xmm2, eax, {ru-sae} turned 16,777,217 into 16,777,218, and {rn-sae} turned the same value from RCX into 16,777,216, the even neighbour;
• neither raised #XM nor set PE, although both results are inexact.

The memory forms have no rounding operand and follow MXCSR: a 64-bit integer below -2^62 was rounded toward zero under FFC0h and set PE. And memory is read as an integer: the four bytes of 1.0f, 3F800000h, became 1,065,353,216.0.

In compiled code#

In our builds at -O2 with -march=x86-64-v3, converting an array of long to float stays one conversion per element: GCC 14 zeroes XMM1 before the loop and runs vcvtsi2ss xmm0, xmm1, qword ptr [...] for each, while Clang 23 converts from memory with XMM15 as the first source and joins four results with VINSERTPS 10h, 20h and 30h. With -march=x86-64-v4 both switch to the packed VCVTQQ2PS. _mm_cvt_roundi32_ss and _mm_cvt_roundi64_ss give the rounding forms, such as vcvtsi2ss xmm0, xmm0, edi, {ru-sae}.

AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows alike two macro-ops for a register source and one for memory, with a latency of 3 cycles; its rows for the legacy CVTSI2SS give no latency.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f32[0] = to_f32(signed(src3))
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSI2SS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS

All 253 AVX instructions

More AVX10.1 instructions

• VCVTPS2DQ
• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI

All 686 AVX10.1 instructions