VCVTSS2SD

VCVTSS2SD is CVTSS2SD with a separate first source: the low single of the last operand becomes the low double of the destination, bits 127:64 come from the first source, and the register is cleared above bit 127. CVTSS2SD’s page covers the conversion itself, which is always exact, and the C promotions that compile to it. The VEX form needs AVX; the EVEX form, with AVX-512F or AVX10.1, adds a write mask on the low double and {sae}, but no rounding mode, since a widened single never needs rounding.

Recorded on Zen 5#

• vcvtss2sd xmm12, xmm6, dword ptr [mem] widened the quiet NaN FFC00005h to FFF80000A0000000h, its fraction moved to the top of the double’s, and left MXCSR at 7F80h.
• With DAZ set (MXCSR 3FC0h), the smallest denormal single gave +0.0 and set no DE.
• vcvtss2sd xmm1{k6}, xmm2, xmm3, {sae}, with bit 0 of K6 clear, kept the low double of XMM1 and still took bits 127:64 from XMM2; with {z} and a clear bit 0, the low double became +0.0.

The first source in compiled code#

In our builds at -O2 with -march=x86-64-v3 or -v4, a float argument returned as a double is vcvtss2sd xmm0, xmm0, xmm0. For a float read from a global array, GCC 14 zeroes XMM0 with VXORPS and converts straight from memory, while Clang 23 loads it with VMOVSS and converts register to register. Summing a float array into a double, GCC zeroes XMM2 once before the loop and names it as the first source of every vcvtss2sd xmm0, xmm2, dword ptr [rax], so no iteration waits for the one before; Clang’s unrolled loop converts each loaded register into itself. Plain C keeps the VEX encoding at -v4; the EVEX forms come from intrinsics such as _mm_mask_cvtss_sd and _mm_cvt_roundss_sd(a, b, _MM_FROUND_NO_EXC).

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike one macro-op with a latency of 3 cycles on pipes FP2 and FP3. VCVTSD2SS narrows the other way.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    xmm1.f64[0] = to_f64(src3.f32[0])
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {sae}: no exception flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSS2SD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU

All 253 AVX instructions

More AVX10.1 instructions

• VCVTPS2PD
• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI

All 686 AVX10.1 instructions