x86-64.net

Instruction

VCVTSS2SH

Converts the low single of the second source to half precision, rounding as MXCSR or the instruction selects; the rest come from the first source.

Extensions
Forms
2 (2 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTSS2SH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTSS2SH xmm {k}{z}, xmm, xmm, {er} VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512EVEX.LIG.NP.MAP5.W0 1D /rAVX10.1 or AVX512_FP16
VCVTSS2SH xmm {k}{z}, xmm, m32 VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512EVEX.LIG.NP.MAP5.W0 1D /rAVX10.1 or AVX512_FP16

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSS2SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvt_roundss_sh __m128h _mm_cvt_roundss_sh(__m128h A, __m128 B, const int R)

VCVTSS2SH xmm, xmm, xmm, {er} EVEX.LIG -mavx512fp16

_mm_cvtss_sh __m128h _mm_cvtss_sh(__m128h __A, __m128 __B)

VCVTSS2SH xmm, xmm, xmm EVEX.LIG -mavx512fp16

_mm_mask_cvt_roundss_sh __m128h _mm_mask_cvt_roundss_sh(__m128h W, __mmask8 U, __m128h A, __m128 B, const int R)

VCVTSS2SH xmm {k}, xmm, xmm, {er} EVEX.LIG -mavx512fp16

_mm_mask_cvtss_sh __m128h _mm_mask_cvtss_sh(__m128h __W, __mmask8 __U, __m128h __A, __m128 __B)

VCVTSS2SH xmm {k}, xmm, xmm EVEX.LIG -mavx512fp16

_mm_maskz_cvt_roundss_sh __m128h _mm_maskz_cvt_roundss_sh(__mmask8 U, __m128h A, __m128 B, const int R)

VCVTSS2SH xmm {k}{z}, xmm, xmm, {er} EVEX.LIG -mavx512fp16

_mm_maskz_cvtss_sh __m128h _mm_maskz_cvtss_sh(__mmask8 __U, __m128h __A, __m128 __B)

VCVTSS2SH xmm {k}{z}, xmm, xmm EVEX.LIG -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_FP16_SCALAR

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.