VCVTSS2SH

VCVTSS2SH converts the low single of its last operand, a register or four bytes of memory, to a half in the low 16 bits of the destination, copying bits 127:16 from the middle operand and clearing bits 128 and up. A half has 11 significant bits and a largest finite value of 65504, so the conversion rounds, by MXCSR.RC or by an {er} mode in the instruction, and can overflow to infinity or underflow to a denormal or zero, with the flags of VCVTPS2PHX, its packed form. It takes a write mask on the low element, and the opcode is 1Dh in EVEX map 5 with no prefix, VCVTPS2PHX’s byte without 66. VADDPH covers AVX512-FP16 and the format.

One rounding for every source#

C’s conversion of a float to _Float16 is this instruction: at -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile it to vcvtss2sh xmm0, xmm0, xmm0, and _mm_cvtss_sh to the two-source form. A double is not taken through a single, which could round twice: both use VCVTSD2SH, its companion for doubles, where with only F16C they call the library’s __truncdfhf2 (see VCVTPS2PH). Storing one float value into every element of a _Float16 array converts it once with VCVTSS2SH and spreads the half with VPBROADCASTW.

Rounding in the instruction#

The F16C form VCVTPS2PH chose its rounding with an immediate; VCVTSS2SH, like the arithmetic of AVX512-FP16, uses MXCSR.RC unless the register form names a mode, which also suppresses every exception: _mm_cvt_roundss_sh(a, b, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC) truncates without setting PE. Intel’s entry for VCVTPS2PHX says its half results are never flushed under FTZ; that for VCVTSS2SH does not mention FTZ. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTSS2SH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f16[0] = to_f16(src3.f32[0])
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSS2SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTPS2PH
• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI

All 686 AVX10.1 instructions