VCVTSS2SI

VCVTSS2SI is the VEX and EVEX form of CVTSS2SI: the low single of an XMM register or of four bytes of memory, converted to a signed 32-bit or 64-bit integer in a general-purpose register and rounded as MXCSR.RC says. CVTSS2SI’s page covers rounding to even, lrintf and the integer indefinite. VCVTSD2SI covers what the encodings add: VEX.vvvv at 1111b, AVX for VEX, and for EVEX, with AVX-512F or AVX10.1, a rounding mode in the instruction that also suppresses exceptions, on a register source only. Zen 5’s recorded cases:

• {evex} vcvtss2si rcx, xmm17, {rz-sae}, under MXCSR 6600H with the invalid exception unmasked, converted the largest single, about 3.4 * 10^38, to the indefinite 8000000000000000h with no #XM and MXCSR unchanged.
• {evex} vcvtss2si eax, xmm7, {rz-sae}, under the same MXCSR with DAZ clear, converted the smallest denormal to 0 without a #XM, though the result is inexact and PE is unmasked.
• {evex} vcvtss2si ecx, dword ptr [mem], under FFC0H with DAZ set, read the largest denormal as zero and gave 0 without setting PE.
• vcvtss2si r14, xmm1 gave 8000000000000000h for 2^63, one past the largest long, and set IE.

Arrays of floats#

In our builds at -O2 with -fno-math-errno, lrintf(x) is vcvtss2si rax, xmm0 in GCC 14 and Clang 23 at -march=x86-64-v3 and x86-64-v4. Rounding a global float array into an int array with lrintf separates them: GCC converts one element at a time from memory at both levels, Clang packs scalar results with VMOVQ, VPUNPCKLQDQ and shuffles at -v3, and at -v4 uses the packed VCVTPS2QQ and narrows with VPMOVQD. _mm_cvt_roundss_si64(v, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC) gives vcvtss2si rax, xmm0, {rz-sae}, a truncation like VCVTTSS2SI with exceptions suppressed.

AMD’s latency spreadsheet for Zen 5 lists it as VCVTSD2SI: two macro-ops, two per cycle, and a latency of 4 cycles in the EVEX row only.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f32[0]
dest.write(cvt_int(a, dest.bits))  # r32: bits 63:32 cleared
# {er}: the form's rounding, not MXCSR.RC, and no flags

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSS2SI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR

All 253 AVX instructions

More AVX10.1 instructions

• VCVTPS2PHX
• VCVTPS2QQ
• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI

All 686 AVX10.1 instructions