VCVTSS2USI instruction (AVX10.1)

VCVTSS2USI converts the low single of an XMM register, or four bytes of memory, to an unsigned integer in a 32-bit or 64-bit general-purpose register, rounding as MXCSR.RC says or as an {er} override on the register form says. It is the rounding form of VCVTTSS2USI and the unsigned partner of VCVTSS2SI, with all ones as the indefinite value for a NaN or a result out of range; a 32-bit destination clears bits 63:32. It came with AVX512F, EVEX only, as did VCVTSD2USI for doubles.

Recorded on Zen 5

2^32. From memory, 2^32 gave FFFFFFFFh in EDX and set IE, and 100000000h in R9, a valid 64-bit result.
Rounding overrides. With {ru-sae}, the smallest normal single gave 1; with {rz-sae}, a negative denormal gave 0. IE was unmasked in MXCSR, and neither case set a flag.

In compiled code

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile _mm_cvtss_u32 and _mm_cvtss_u64 to VCVTSS2USI. For (unsigned)rintf(x) they round with VRNDSCALESS in GCC or VROUNDSS in Clang, and truncate with VCVTTSS2USI.

AMD’s Zen 5 latency spreadsheet gives two macro-ops, on pipes FP2/3 and FP4/5, and 4 cycles, as for VCVTSD2USI.

Forms

Every encoding of VCVTSS2USI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VCVTSS2USI r32, xmm, {er}` VCVTSS2USI_GPR32u32_XMMf32_AVX512	`EVEX.LIG.F3.0F.W0 79 /r`	AVX10.1 or AVX512F
`VCVTSS2USI r32, m32` VCVTSS2USI_GPR32u32_MEMf32_AVX512	`EVEX.LIG.F3.0F.W0 79 /r`	AVX10.1 or AVX512F
`VCVTSS2USI r64, xmm, {er}` 64-bit mode only VCVTSS2USI_GPR64u64_XMMf32_AVX512	`EVEX.LIG.F3.0F.W1 79 /r`	AVX10.1 or AVX512F
`VCVTSS2USI r64, m32` 64-bit mode only VCVTSS2USI_GPR64u64_MEMf32_AVX512	`EVEX.LIG.F3.0F.W1 79 /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`r32, xmm, {er}`	`r32, m32`	`r64, xmm, {er}`	`r64, m32`
Skylake-SP, Ice Lake	6 / 1p01	11 / 1p01	7 / 1p015	12 / 1p01
Sapphire Rapids	7 / 1p01	12 / 1p01	8 / 1p015	12 / 1p01
Zen 4	5 / 2.5FP2 FP3	12 / 2.5FP2 FP3	5 / 2.5FP2 FP3	12 / 2.5FP2 FP3

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low single of xmm2 is converted, and the integer goes to r32.

r32 receives the conversion of single 0 of xmm2: r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f32[0]
dest.write(cvt_uint(a, dest.bits))  # r32: bits 63:32 cleared
# {er}: the form's rounding, not MXCSR.RC, and no flags

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VCVTSS2USI r32, xmm/m32, {er}` `VCVTSS2USI r64, xmm/m32, {er}` 64-bit mode only
`r32/64`	explicit	write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSS2USI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvt_roundss_u32` `unsigned int _mm_cvt_roundss_u32(__m128 A, const int R)`	`VCVTSS2USI r32, xmm, {er}` EVEX.LIG -mavx512f
`_mm_cvt_roundss_u64` `unsigned long long _mm_cvt_roundss_u64(__m128 A, const int R)`	`VCVTSS2USI r64, xmm, {er}` EVEX.LIG -mavx512f
`_mm_cvtss_u32` `unsigned int _mm_cvtss_u32(__m128 __A)`	`VCVTSS2USI r32, xmm` EVEX.LIG -mavx512f
`_mm_cvtss_u64` `unsigned long long _mm_cvtss_u64(__m128 __A)`	`VCVTSS2USI r64, xmm` EVEX.LIG -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512F_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX512F_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Recorded on Zen 5#

In compiled code#