x86-64.net

Instruction

VCVTSS2USI

Converts the low single to an unsigned 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects.

Extensions
Forms
4 (4 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTSS2USI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTSS2USI r32, xmm, {er} VCVTSS2USI_GPR32u32_XMMf32_AVX512EVEX.LIG.F3.0F.W0 79 /rAVX10.1 or AVX512F
VCVTSS2USI r32, m32 VCVTSS2USI_GPR32u32_MEMf32_AVX512EVEX.LIG.F3.0F.W0 79 /rAVX10.1 or AVX512F
VCVTSS2USI r64, xmm, {er} 64-bit mode only VCVTSS2USI_GPR64u64_XMMf32_AVX512EVEX.LIG.F3.0F.W1 79 /rAVX10.1 or AVX512F
VCVTSS2USI r64, m32 64-bit mode only VCVTSS2USI_GPR64u64_MEMf32_AVX512EVEX.LIG.F3.0F.W1 79 /rAVX10.1 or AVX512F

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTSS2USI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvt_roundss_u32 unsigned int _mm_cvt_roundss_u32(__m128 A, const int R)

VCVTSS2USI r32, xmm, {er} EVEX.LIG -mavx512f

_mm_cvt_roundss_u64 unsigned long long _mm_cvt_roundss_u64(__m128 A, const int R)

VCVTSS2USI r64, xmm, {er} EVEX.LIG -mavx512f

_mm_cvtss_u32 unsigned int _mm_cvtss_u32(__m128 __A)

VCVTSS2USI r32, xmm EVEX.LIG -mavx512f

_mm_cvtss_u64 unsigned long long _mm_cvtss_u64(__m128 __A)

VCVTSS2USI r64, xmm EVEX.LIG -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512F_SCALAR

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.