VCVTTBF162IBS

VCVTTBF162IBS converts each bfloat16 value to a signed byte, truncating toward zero, and saturates: above 127 gives 7Fh, below -128 gives 80h, and a NaN gives 0, each result in the low byte of its word with the high byte cleared. Its opcode is 68h with the F2 prefix in EVEX map 5, one below the rounding VCVTBF162IBS, whose page covers what the bfloat16 forms share: MXCSR is neither read nor written, no exception is reported, and there is no {sae} operand, since there is nothing to suppress. VCVTPS2IBS describes the family.

With 8 significant bits, bfloat16 has no fractions from 128 up in magnitude and steps of 1/2 from 64 to 128, so truncation and rounding differ only for the smaller values: 2.5 and 2.75 both truncate to 2, where VCVTBF162IBS gives 2 and 3, and 127.5 truncates to 127, where rounding gives 128 and so saturates to 127 as well.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles _mm512_ipcvtts_bf16_epi8 to vcvttbf162ibs zmm0, zmm0. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = src2.bf16[i]
        zmm1.w[i] = cvtts_int(a, 8) & 0xFF
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# m16bcst: src2.bf16[i] is the m16 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; denormal inputs read as zero

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTBF162IBS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS
• VFMADD132BF16

All 96 AVX10.2 instructions