VCVTTPD2DQ

VCVTTPD2DQ converts doubles to signed doublewords, truncating toward zero, into a register half as wide as its source. The legacy CVTTPD2DQ page covers the truncation, the integer indefinite 80000000H, the AT&T suffixes vcvttpd2dqx and vcvttpd2dqy, and how GCC joins two halves, and VCVTTPS2DQ explains {sae}, which this form shares. What the double source adds:

Every doubleword fits from below#

A double holds every 32-bit integer and the fractions around them, so the edge of the range is visible here as it is not with singles. In the cases recorded on Zen 5, 2,147,483,647.9999998 truncated to 7FFFFFFFH, the largest doubleword, while 2^31 gave 80000000H, the indefinite value, and -2^31 also 80000000H, this time as a real result. Rounding to nearest, VCVTPD2DQ would have turned the first into the indefinite value too.

Masks and broadcast#

Each mask bit selects a result doubleword, eight for a zmm source. With K4 holding CAH, vcvttpd2dq ymm24{k4}, zmm3, {sae} wrote elements 1, 3, 6 and 7 (2^31, 2,147,483,647.9999998, 10^300 and 10^-300 became 80000000H, 7FFFFFFFH, 80000000H and 0) and kept the rest. A broadcast double, {1to2}, {1to4} or {1to8} in AT&T syntax, converts one value into every element. With MXCSR 0, every exception unmasked, {sae} let a signaling NaN through as 80000000H without #XM.

In compiled code#

In our builds at -O2, Clang 23 compiles out[i] = (int)in[i] over doubles to one VCVTTPD2DQ per 32 bytes, ymm to xmm, each result stored on its own for -march=x86-64-v3 and x86-64-v4, and zmm to ymm for znver5; GCC 14 joins pairs with VINSERTI128, or VINSERTI32X8 for x86-64-v4. AVX10.2’s VCVTTPD2DQS saturates instead: 7FFFFFFFH for 2^31 rather than the indefinite value.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = src2.f64[i]
        ymm1.d[i] = cvtt_int(a, 32)
    elif zeroing:
        ymm1.d[i] = 0
    # else: ymm1.d[i] keeps its value
for i in range(VL // 64, 4):
    ymm1.d[i] = 0
# m64bcst: src2.f64[i] is the m64 for every i
# {sae}: no exception flags
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPD2DQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU

All 253 AVX instructions

More AVX10.1 instructions

• VCVTPS2UDQ
• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD

All 686 AVX10.1 instructions