VCVTTPD2DQS

VCVTTPD2DQS converts doubles to signed doublewords, truncating toward zero, and saturates where VCVTTPD2DQ gives the integer indefinite 80000000h: a value of 2^31 or more becomes 7FFFFFFFh, one at or below -2^31 - 1 becomes 80000000h, and a NaN becomes 0. VCVTTPS2DQS’s page explains why languages that define their casts want this. As in VCVTTPD2DQ, the result is half as wide as the source: two, four or eight doubles from an xmm, ymm or zmm register or memory give an xmm or ymm result, the upper part of the destination cleared. It belongs to AVX10.2: opcode 6Dh in EVEX map 5, no prefix, W1, with a write mask, a broadcast double and {sae} on the 512-bit form.

Exceptions still raised#

Saturation does not silence the invalid exception. In the AVX10.2 specification’s helper (revision 7.0), a NaN, an infinity or an out-of-range value sets IE, and an in-range value that loses a fraction sets PE. With IE masked, as it normally is, the saturated value is written; unmasked, the instruction faults like any other.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles _mm512_cvtts_pd_epi32 to vcvttpd2dqs ymm0, zmm0, but never uses the instruction for C code: (int)x over a double array stays VCVTTPD2DQ, and a loop that saturates by hand, x != x ? 0 : x >= 2147483647.0 ? INT_MAX : x <= -2147483648.0 ? INT_MIN : (int)x, becomes VMAXPD, VCMPLEPD, VCMPORDPD, VCVTTPD2DQ and masked moves. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f64[i]
        ymm1.d[i] = cvtts_int(a, 32)
    elif zeroing:
        ymm1.d[i] = 0
    # else: ymm1.d[i] keeps its value
for i in range(VL // 64, 4):
    ymm1.d[i] = 0
# m64bcst: src2.f64[i] is the m64 for every i
# {sae}: no exception flags
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPD2DQS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16

All 96 AVX10.2 instructions