VCVTTPD2QQ

VCVTTPD2QQ converts each double of an XMM, YMM or ZMM register, or of memory, to a signed quadword, truncating toward zero whatever MXCSR.RC says: the vector form of C’s cast from double to long. It came with AVX512DQ. Before it no instruction converted more than one double to a 64-bit integer at a time, as CVTTPD2DQ stops at 32 bits, so the vectorized cast needs AVX-512.

What the compilers do#

GCC 14 and Clang 23 at -O2 compile a loop of out[i] = (long)in[i] with one CVTTSD2SI per element, with and without -mavx2; Clang joins pairs of results with VPUNPCKLQDQ. With -march=x86-64-v4 both use VCVTTPD2QQ, GCC on ZMM registers, eight doubles at a time, and Clang on YMM registers, four at a time.

Range#

A NaN, an infinity or a double whose integer part lies outside -2^63 to 2^63 minus 1 gives 8000000000000000H, the integer indefinite, and sets IE, or raises #XM where IE is unmasked. Every double of magnitude 2^52 or more is already an integer, so near the ends of the range nothing is truncated: the largest double below 2^63 is 2^63 minus 1024, which converts exactly, and 2^63 itself is out of range. The cases recorded on Zen 5 show both kinds of results: the largest finite doubles of either sign gave the indefinite and set IE, 9,223,371,487,098,961,920 converted to 7FFFFF8000000000H, -1.0 to all ones, and 1.0000000000000002 to 1 with PE set, although MXCSR said to round up.

EVEX features#

As an EVEX instruction it writes under a mask, merging or zeroing the elements left out, can broadcast one double from memory to every element, and in its 512-bit register form takes {sae}, which turns off the exception flags: Zen 5 converted under {sae} with MXCSR left as it was.

Related conversions: VCVTTPD2UQQ gives unsigned quadwords, VCVTPD2QQ rounds as MXCSR says, VCVTTPS2QQ widens singles, and AVX10.2’s VCVTTPD2QQS saturates out-of-range values instead of giving the indefinite. AMD’s Zen 5 guide lists VCVTTPD2QQ as one macro-op with a latency of three cycles at every width.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f64[i]
        zmm1.q[i] = cvtt_int(a, 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.f64[i] is the m64 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPD2QQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTPS2UQQ
• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH

All 686 AVX10.1 instructions