VCVTTPD2QQS

VCVTTPD2QQS converts doubles to signed quadwords, truncating toward zero, and saturates where VCVTTPD2QQ gives the indefinite 8000000000000000h: values of 2^63 or more become 7FFFFFFFFFFFFFFFh, values below -2^63 become 8000000000000000h, and a NaN becomes 0. VCVTTPS2DQS’s page covers the idea. Source and result have the same width, two, four or eight elements. It belongs to AVX10.2: opcode 6Dh in EVEX map 5 with a 66 prefix and W1, the same opcode as VCVTTPD2DQS with a prefix added, with a write mask, a broadcast double and {sae} on the 512-bit form. NaNs, infinities and out-of-range values still set IE, and a lost fraction sets PE.

A slip in the helper#

The specification’s helper for this conversion (revision 7.0) does not match its own description: after the test for large positive values, its branch for the minimum is taken for any value up to +2^63, which would turn every remaining input into 8000000000000000h. The description and the instruction’s name both mean the saturating conversion above. The single-precision helper behind VCVTTPS2QQS has a different slip.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles _mm512_cvtts_pd_epi64 to vcvttpd2qqs zmm0, zmm0; a loop converting doubles to int64_t keeps VCVTTPD2QQ. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f64[i]
        zmm1.q[i] = cvtts_int(a, 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.f64[i] is the m64 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPD2QQS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16

All 96 AVX10.2 instructions