Instruction
VCVTTPD2QQS
Converts packed doubles to 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VCVTTPD2QQS xmm {k}{z}, xmm
VCVTTPD2QQS_XMMi64_MASKmskw_XMMf64_AVX512 | EVEX.128.66.MAP5.W1 6D /r | AVX10.2 |
VCVTTPD2QQS xmm {k}{z}, m128/m64bcst
VCVTTPD2QQS_XMMi64_MASKmskw_MEMf64_AVX512 | EVEX.128.66.MAP5.W1 6D /r | AVX10.2 |
VCVTTPD2QQS ymm {k}{z}, ymm
VCVTTPD2QQS_YMMi64_MASKmskw_YMMf64_AVX512 | EVEX.256.66.MAP5.W1 6D /r | AVX10.2 |
VCVTTPD2QQS ymm {k}{z}, m256/m64bcst
VCVTTPD2QQS_YMMi64_MASKmskw_MEMf64_AVX512 | EVEX.256.66.MAP5.W1 6D /r | AVX10.2 |
VCVTTPD2QQS zmm {k}{z}, zmm, {sae}
VCVTTPD2QQS_ZMMi64_MASKmskw_ZMMf64_AVX512 | EVEX.512.66.MAP5.W1 6D /r | AVX10.2 |
VCVTTPD2QQS zmm {k}{z}, m512/m64bcst
VCVTTPD2QQS_ZMMi64_MASKmskw_MEMf64_AVX512 | EVEX.512.66.MAP5.W1 6D /r | AVX10.2 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VCVTTPD2QQS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cvtts_pd_epi64
__m128i _mm_cvtts_pd_epi64(__m128d __A) |
|
_mm_mask_cvtts_pd_epi64
__m128i _mm_mask_cvtts_pd_epi64(__m128i __W, __mmask8 __U, __m128d __A) |
|
_mm_maskz_cvtts_pd_epi64
__m128i _mm_maskz_cvtts_pd_epi64(__mmask8 __U, __m128d __A) |
|
_mm256_cvtts_pd_epi64
__m256i _mm256_cvtts_pd_epi64(__m256d __A) |
|
_mm256_mask_cvtts_pd_epi64
__m256i _mm256_mask_cvtts_pd_epi64(__m256i __W, __mmask8 __U, __m256d __A) |
|
_mm256_maskz_cvtts_pd_epi64
__m256i _mm256_maskz_cvtts_pd_epi64(__mmask8 __U, __m256d __A) |
|
_mm512_cvtts_pd_epi64
__m512i _mm512_cvtts_pd_epi64(__m512d __A) |
|
_mm512_cvtts_roundpd_epi64
__m512i _mm512_cvtts_roundpd_epi64(__m512d __A, const int __R) |
|
_mm512_mask_cvtts_pd_epi64
__m512i _mm512_mask_cvtts_pd_epi64(__m512i __W, __mmask8 __U, __m512d __A) |
|
_mm512_mask_cvtts_roundpd_epi64
__m512i _mm512_mask_cvtts_roundpd_epi64(__m512i __W, __mmask8 __U, __m512d __A, const int __R) |
|
_mm512_maskz_cvtts_pd_epi64
__m512i _mm512_maskz_cvtts_pd_epi64(__mmask8 __U, __m512d __A) |
|
_mm512_maskz_cvtts_roundpd_epi64
__m512i _mm512_maskz_cvtts_roundpd_epi64(__mmask8 __U, __m512d __A, const int __R) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_SAT_CVT_DS_128 | AVX10.2 | Nova Lake, Diamond Rapids |
AVX512_SAT_CVT_DS_256 | AVX10.2 | Nova Lake, Diamond Rapids |
AVX512_SAT_CVT_DS_512 | AVX10.2 | Nova Lake, Diamond Rapids |
More AVX10.2 instructions
- VCVT2PH2HF8S
- VCVT2PS2PHX
- VCVTBF162IBS
- VCVTBF162IUBS
- VCVTBIASPH2BF8
- VCVTBIASPH2BF8S
- VCVTBIASPH2HF8
- VCVTBIASPH2HF8S
- VCVTHF82PH
- VCVTPH2BF8
- VCVTPH2BF8S
- VCVTPH2HF8
- VCVTPH2HF8S
- VCVTPH2IBS
- VCVTPH2IUBS
- VCVTPS2IBS
- VCVTPS2IUBS
- VCVTTBF162IBS
- VCVTTBF162IUBS
- VCVTTPD2DQS
- VCVTTPD2UDQS
- VCVTTPD2UQQS
- VCVTTPH2IBS
- VCVTTPH2IUBS
- VCVTTPS2DQS
- VCVTTPS2IBS
- VCVTTPS2IUBS
- VCVTTPS2QQS
- VCVTTPS2UDQS
- VCVTTPS2UQQS
- VCVTTSD2SIS
- VCVTTSD2USIS
- VCVTTSS2SIS
- VCVTTSS2USIS
- VDIVBF16
- VDPPHPS
- VFMADD132BF16
- VFMADD213BF16
- VFMADD231BF16
- VFMSUB132BF16
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.