VCVTTPD2UDQ

VCVTTPD2UDQ truncates doubles toward zero to unsigned doublewords: 8 doubles of a ZMM register become 8 doublewords in a YMM register, 4 fill an XMM register and 2 fill its low 64 bits, with the rest of the destination cleared. It is the unsigned partner of VCVTTPD2DQ, with the range 0 to 2^32 - 1 and FFFFFFFFh as the indefinite value, and the double-precision sibling of VCVTTPS2UDQ. It came with AVX512F; the 512-bit register form takes {sae}.

Recorded on Zen 5#

• Truncation. 4.0, 1.5, 3.0, 0.5 and 0.1 gave 4, 1, 3, 0 and 0; -2.5 gave FFFFFFFFh, since it truncates to -2, which is out of range.
• The same bits, two meanings. 2^32 - 0.5 gave FFFFFFFFh as a valid result, setting only PE; a huge double and a quiet NaN gave the same FFFFFFFFh as the indefinite and set IE. 2^31 minus a tiny fraction gave 7FFFFFFFh.
• The upper part. The XMM form, {evex} vcvttpd2udq xmm0, xmm31, wrote its two doublewords and cleared XMM0 from bit 64 up.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile u[i] = (uint32_t)d[i] to VCVTTPD2UDQ from memory. GCC converts two ZMM loads to YMM halves and joins them with VINSERTI32X8; Clang converts YMM loads to XMM registers and stores each. _mm512_cvttpd_epu32 is the ZMM form. With -march=x86-64-v3 both build the conversion from VCVTTPD2DQ, converting a second time after subtracting 2^31 with VSUBPD and merging the two results, as for singles on VCVTTPS2UDQ’s page.

AMD’s Zen 5 latency spreadsheet gives the XMM source one macro-op and 3 cycles, and the YMM and ZMM sources two macro-ops, with 6 and 7 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f64[i]
        ymm1.d[i] = cvtt_uint(a, 32)
    elif zeroing:
        ymm1.d[i] = 0
    # else: ymm1.d[i] keeps its value
for i in range(VL // 64, 4):
    ymm1.d[i] = 0
# m64bcst: src2.f64[i] is the m64 for every i
# {sae}: no exception flags
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPD2UDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTQQ2PD
• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS

All 686 AVX10.1 instructions