VCVTTPD2UQQ

VCVTTPD2UQQ converts each double of an XMM, YMM or ZMM register, or of memory, to an unsigned quadword, truncating toward zero whatever MXCSR.RC says: the vector form of C’s cast from double to uint64_t. It is the unsigned partner of VCVTTPD2QQ, which came with it in AVX512DQ, and the vector form of VCVTTSD2USI. A value that truncates to 0 to 2^64 - 1 converts, so -0.5 gives 0; anything else, NaNs and infinities included, gives FFFFFFFFFFFFFFFFh and sets IE. VCVTPD2UQQ rounds instead, and VCVTTPD2UDQ converts to doublewords.

Recorded on Zen 5#

• Infinities. {evex} vcvttpd2uqq xmm5, xmm5 turned +infinity and -infinity both into FFFFFFFFFFFFFFFFh and set IE.
• 2^63 is valid. 2^63 gave 8000000000000000h, the signed conversion’s indefinite value and here an ordinary result, while a double near 10^300 gave FFFFFFFFFFFFFFFFh with IE.
• With {sae}. In vcvttpd2uqq zmm5{k5}, zmm5, {sae}, with IE unmasked, the double just below 2^31 gave 7FFFFFFFh, 1.0000000000000002 gave 1 and -2^63 gave FFFFFFFFFFFFFFFFh, without a fault or a flag.
• Precision. A broadcast 0.5 gave 0 and set PE.

In compiled code#

At -O2 with -march=x86-64-v4, both compilers vectorize u[i] = (uint64_t)d[i] with VCVTTPD2UQQ, GCC 14 on ZMM registers and Clang 23 on YMM registers, and use it after a rounding instruction for (uint64_t)rint(d[i]). A single cast is VCVTTSD2USI. _mm512_cvttpd_epu64 is one VCVTTPD2UQQ.

AMD’s Zen 5 latency spreadsheet gives every width one macro-op on pipe FP2 or FP3 and 3 cycles, as for VCVTTPD2QQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f64[i]
        zmm1.q[i] = cvtt_uint(a, 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.f64[i] is the m64 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPD2UQQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTQQ2PH
• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD

All 686 AVX10.1 instructions