VCVTTPH2DQ

VCVTTPH2DQ converts halves to signed doublewords, truncating toward zero whatever MXCSR.RC says: the vector form of C’s conversion from _Float16 to int. Like VCVTPH2DQ, the rounding form, it reads 4, 8 or 16 halves from the low 64, 128 or 256 bits of the source and fills an XMM, YMM or ZMM register. The opcode is 5Bh with the F3 prefix in EVEX map 5, where VCVTTPS2DQ has F3 5Bh in the 0F map; that page covers truncation for singles.

Truncation for halves#

Every finite half, at most 65504 in magnitude, fits a doubleword, so the integer indefinite 80000000h with IE comes only from a NaN or an infinity; 2.75 gives 2 and -2.75 gives -2, setting PE. The 512-bit register form takes {sae}, which suppresses the flags but cannot change the rounding, since there is none to choose. A half can be broadcast from memory, and a write mask merges or zeroes doublewords.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, a[i] = h[i] from a _Float16 array to an int array becomes VCVTTPH2DQ in GCC 14 and Clang 23. GCC loads 32 halves into a ZMM register and converts its two halves into two ZMM results, taking the upper one out with VEXTRACTI64X4; Clang loads 64 bits at a time with VMOVSD and converts on XMM registers, without folding the load into the conversion. With -fno-math-errno, Clang compiles (int)nearbyintf(h[i]) to VRNDSCALEPH with immediate 12, which rounds by MXCSR.RC without reporting inexact, followed by VCVTTPH2DQ. A single value is converted with VCVTTSH2SI. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTTPH2DQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = src2.f16[i]
        zmm1.d[i] = cvtt_int(a, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Half); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPH2DQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTQQ2PS
• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH

All 686 AVX10.1 instructions