VCVTTPH2IBS

VCVTTPH2IBS converts each half-precision value to a signed byte, truncating toward zero, and saturates: 128 or more gives 7Fh, -129 or less gives 80h, and a NaN gives 0, each result in the low byte of its word with the high byte cleared. 127.9 gives 127 and -128.9 gives -128, with PE alone; 128, -129, infinities and NaNs set IE. Its opcode is 68h without a prefix in EVEX map 5, one below the rounding VCVTPH2IBS, and the 512-bit register form takes {sae}. VCVTPS2IBS describes the family, and VCVTTPH2W truncates halves to words, with 8000h for anything out of range.

The helper’s shift#

The specification’s description truncates the half’s value. Its helper function for this instruction instead converts the half shifted left by 16 bits, the step its bfloat16 helpers use to turn a bfloat16 value into a single; for a half that shift does not keep the value, and the helper names the conversion as one from half precision anyway. The description is the plain reading.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles _mm512_ipcvtts_ph_epi8 to vcvttph2ibs zmm0, zmm0. A loop that clamps _Float16 values to -128 and 127 and stores them as int8_t keeps VMAXPH, VMINPH and VCVTTPH2W, then packs the words with VPMOVWB and VPERMB. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = src2.f16[i]
        zmm1.w[i] = cvtts_int(a, 8) & 0xFF
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPH2IBS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16

All 96 AVX10.2 instructions