VCVTTPH2IUBS

VCVTTPH2IUBS converts each half-precision value to an unsigned byte, truncating toward zero, and saturates: 256 or more gives FFh, -1 or less gives 0, and a NaN gives 0, each result in the low byte of its word with the high byte cleared. Values between -1 and 0 truncate to 0 with PE alone, and 255.9 gives 255; 256, -1, infinities and NaNs set IE. Its opcode is 6Ah without a prefix in EVEX map 5, beside 68h for the signed VCVTTPH2IBS, and the 512-bit register form takes {sae}. VCVTPS2IBS describes the family, and VCVTTPH2UW truncates halves to unsigned words.

A bfloat16 test in the helper#

The specification’s helper function for this instruction tests the half for NaN and for 255 or more, but its test for zero or less names the source as a bfloat16 value, a slip from the bfloat16 helpers beside it. The description has the plain rule: anything too small gives 0.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles _mm512_ipcvtts_ph_epu8 to vcvttph2iubs zmm0, zmm0, and _mm_ipcvtts_ph_epu8 to vcvttph2iubs xmm0, xmm0. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = src2.f16[i]
        zmm1.w[i] = cvtts_uint(a, 8)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPH2IUBS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16

All 96 AVX10.2 instructions