VCVTTPH2QQ

VCVTTPH2QQ converts halves to signed quadwords, truncating toward zero: the vector form of C’s conversion from _Float16 to int64_t. The source is a quarter as wide as the destination, so the XMM form reads 32 bits for 2 quadwords, the YMM form 64 bits for 4 and the ZMM form 128 bits for 8. The opcode is 7Ah with the 66 prefix in EVEX map 5, as VCVTTPS2QQ has it in the 0F map; VCVTTPD2QQ covers the truncation to quadwords from doubles, and VCVTPH2QQ is the rounding form.

Range#

A truncated finite half lies between -65504 and 65504, so it always fits: the indefinite value 8000000000000000h with IE comes only from a NaN or an infinity, and a dropped fraction sets PE. The 512-bit register form takes {sae}, a half can be broadcast from memory, and a write mask merges or zeroes quadwords.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, Clang 23 converts a _Float16 array into an int64_t array with VCVTTPH2QQ on XMM registers, loading 32 bits at a time with VMOVSS for each pair of quadwords. GCC 14 stays scalar, converting each element straight from memory with VCVTTSH2SI and a 64-bit destination, as it stays scalar the other way, from quadwords to halves (see VCVTQQ2PH). _mm512_cvttph_epi64 and _mm512_cvtt_roundph_epi64 are the intrinsics. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTTPH2QQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f16[i]
        zmm1.q[i] = cvtt_int(a, 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Quarter); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPH2QQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTSD2SH
• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS

All 686 AVX10.1 instructions