x86-64.net

Instruction

VCVTTPH2UDQ

Converts packed half-precision values to unsigned doublewords, truncating toward zero.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTTPH2UDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTTPH2UDQ xmm {k}{z}, xmm VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512EVEX.128.NP.MAP5.W0 78 /rAVX10.1 or AVX512_FP16 + AVX512VL
VCVTTPH2UDQ xmm {k}{z}, m128/m16bcst VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512EVEX.128.NP.MAP5.W0 78 /rAVX10.1 or AVX512_FP16 + AVX512VL
VCVTTPH2UDQ ymm {k}{z}, xmm VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512EVEX.256.NP.MAP5.W0 78 /rAVX10.1 or AVX512_FP16 + AVX512VL
VCVTTPH2UDQ ymm {k}{z}, m256/m16bcst VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512EVEX.256.NP.MAP5.W0 78 /rAVX10.1 or AVX512_FP16 + AVX512VL
VCVTTPH2UDQ zmm {k}{z}, ymm, {sae} VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512EVEX.512.NP.MAP5.W0 78 /rAVX10.1 or AVX512_FP16
VCVTTPH2UDQ zmm {k}{z}, m512/m16bcst VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512EVEX.512.NP.MAP5.W0 78 /rAVX10.1 or AVX512_FP16

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPH2UDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvttph_epu32 __m128i _mm_cvttph_epu32(__m128h __A)

VCVTTPH2UDQ xmm, xmm EVEX.128 -mavx512fp16 -mavx512vl

_mm_mask_cvttph_epu32 __m128i _mm_mask_cvttph_epu32(__m128i __W, __mmask8 __U, __m128h __A)

VCVTTPH2UDQ xmm {k}, xmm EVEX.128 -mavx512fp16 -mavx512vl

_mm_maskz_cvttph_epu32 __m128i _mm_maskz_cvttph_epu32(__mmask8 __U, __m128h __A)

VCVTTPH2UDQ xmm {k}{z}, xmm EVEX.128 -mavx512fp16 -mavx512vl

_mm256_cvttph_epu32 __m256i _mm256_cvttph_epu32(__m128h __A)

VCVTTPH2UDQ ymm, xmm EVEX.256 -mavx512fp16 -mavx512vl

_mm256_mask_cvttph_epu32 __m256i _mm256_mask_cvttph_epu32(__m256i __W, __mmask8 __U, __m128h __A)

VCVTTPH2UDQ ymm {k}, xmm EVEX.256 -mavx512fp16 -mavx512vl

_mm256_maskz_cvttph_epu32 __m256i _mm256_maskz_cvttph_epu32(__mmask8 __U, __m128h __A)

VCVTTPH2UDQ ymm {k}{z}, xmm EVEX.256 -mavx512fp16 -mavx512vl

_mm512_cvtt_roundph_epu32 __m512i _mm512_cvtt_roundph_epu32(__m256h A, const int R)

VCVTTPH2UDQ zmm, ymm, {sae} EVEX.512 -mavx512fp16

_mm512_cvttph_epu32 __m512i _mm512_cvttph_epu32(__m256h __A)

VCVTTPH2UDQ zmm, ymm EVEX.512 -mavx512fp16

_mm512_mask_cvtt_roundph_epu32 __m512i _mm512_mask_cvtt_roundph_epu32(__m512i W, __mmask16 U, __m256h A, const int R)

VCVTTPH2UDQ zmm {k}, ymm, {sae} EVEX.512 -mavx512fp16

_mm512_mask_cvttph_epu32 __m512i _mm512_mask_cvttph_epu32(__m512i __W, __mmask16 __U, __m256h __A)

VCVTTPH2UDQ zmm {k}, ymm EVEX.512 -mavx512fp16

_mm512_maskz_cvtt_roundph_epu32 __m512i _mm512_maskz_cvtt_roundph_epu32(__mmask16 U, __m256h A, const int R)

VCVTTPH2UDQ zmm {k}{z}, ymm, {sae} EVEX.512 -mavx512fp16

_mm512_maskz_cvttph_epu32 __m512i _mm512_maskz_cvttph_epu32(__mmask16 __U, __m256h __A)

VCVTTPH2UDQ zmm {k}{z}, ymm EVEX.512 -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_FP16_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16 + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_FP16_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16 + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_FP16_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.