VCVTTPH2UDQ

VCVTTPH2UDQ converts halves to unsigned doublewords, truncating toward zero: the vector form of C’s conversion from _Float16 to uint32_t. It reads 4, 8 or 16 halves from the low 64, 128 or 256 bits of the source into an XMM, YMM or ZMM register. The opcode is 78h without a prefix in EVEX map 5, the byte of VCVTTPS2UDQ in the 0F map, whose page covers the unsigned range for singles; VCVTTPH2DQ is the signed form and VCVTPH2UDQ the rounding one.

Small negatives become zero#

Truncation moves toward zero, so a negative half above -1, such as -0.75, becomes 0 with only the precision flag, where the rounding form in round to nearest turns it into -1 and fails. From -1 down, and for NaN and the infinities, Intel’s entry raises the invalid exception and, masked, returns FFFFFFFFh; every half from 0 to 65504 fits. The 512-bit register form takes {sae}, a half can be broadcast from memory, and a write mask merges or zeroes doublewords.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, u[i] = h[i] from a _Float16 array to a uint32_t array becomes VCVTTPH2UDQ in GCC 14, two ZMM results from each 64-byte load with VEXTRACTI64X4 between them, and in Clang 23 on XMM registers after 64-bit VMOVSD loads. A single value is converted with VCVTTSH2USI. With -fno-math-errno, (uint32_t)rintf(h[i]) adds VRNDSCALEPH before VCVTTPH2UDQ in Clang. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTTPH2UDQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = src2.f16[i]
        zmm1.d[i] = cvtt_uint(a, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Half); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPH2UDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTSD2SI
• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD

All 686 AVX10.1 instructions