VCVTTPH2UQQ

VCVTTPH2UQQ converts halves to unsigned quadwords, truncating toward zero: 2, 4 or 8 halves from the low 32, 64 or 128 bits of the source into an XMM, YMM or ZMM register. The opcode is 78h with the 66 prefix in EVEX map 5, where VCVTTPH2UDQ has no prefix; VCVTTPH2QQ is the signed form, VCVTPH2UQQ the rounding one, and VCVTTPD2UQQ does the same for doubles.

Range#

Every half from 0 to 65504 fits, and so does a negative half above -1, which truncates to 0 with only the precision flag. From -1 down, and for NaN and the infinities, Intel’s entry raises the invalid exception and, masked, returns FFFFFFFFFFFFFFFFh, a value no finite half produces. The 512-bit register form takes {sae}, a half can be broadcast from memory, and a write mask merges or zeroes quadwords.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, a loop converting a _Float16 array into a uint64_t array becomes VCVTTPH2UQQ on XMM registers in Clang 23, after 32-bit VMOVSS loads, and stays scalar in GCC 14, one VCVTTSH2USI from memory per element. _mm512_cvttph_epu64 gives vcvttph2uqq zmm0, xmm0 in both. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTTPH2UQQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f16[i]
        zmm1.q[i] = cvtt_uint(a, 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Quarter); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPH2UQQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTSD2SS
• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH

All 686 AVX10.1 instructions