VCVTTPH2UW

VCVTTPH2UW converts halves to unsigned words, truncating toward zero, element for element: 8, 16 or 32 at a time, the vector form of C’s conversion from _Float16 to unsigned short. The opcode is 7Ch without a prefix in EVEX map 5, where VCVTTPH2W has 66; VCVTPH2UW rounds instead and VCVTUW2PH goes the other way. As for VCVTTPH2W, Intel’s title omits “with truncation”.

Range#

Every half from 0 to 65504 fits an unsigned word, and so does a negative half above -1, which truncates to 0 with only the precision flag. From -1 down, and for NaN and the infinities, the invalid exception is raised and, masked, the result is FFFFh, which no finite half produces. So a non-negative half array converts to unsigned words without any value out of range, which signed words cannot promise. The 512-bit register form takes {sae}, a half can be broadcast from memory, and a write mask merges or zeroes words.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, u[i] = h[i] from a _Float16 array to a uint16_t array becomes VCVTTPH2UW in GCC 14, 32 halves from memory per ZMM conversion, and in Clang 23, which converts on XMM registers after 64-bit loads and joins the results with VPERMT2Q. _mm512_cvttph_epu16 gives the register form in both. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTTPH2UW.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = src2.f16[i]
        zmm1.w[i] = cvtt_uint(a, 16)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPH2UW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTSD2USI
• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS

All 686 AVX10.1 instructions