VCVTTPH2W

VCVTTPH2W converts halves to signed words, truncating toward zero, element for element: 8, 16 or 32 at a time. It is the vector form of C’s conversion from _Float16 to short and has no single-precision counterpart, since no SSE or AVX conversion produces words. The opcode is 7Ch with the 66 prefix in EVEX map 5, next to 7Dh for the rounding VCVTPH2W, whose page covers the word range; VCVTW2PH goes the other way. Intel’s entry is titled without the “with truncation” of the other truncating FP16 entries, though its text and operation truncate.

Range#

A half reaches 65504 and a word 32767, so any half of 32768 or more, and any below -32768, raises the invalid exception and, masked, gives 8000h, the same pattern as the valid -32768. Below 32768 the halves are 16 apart, so 32752 is the largest that converts; a fraction is dropped toward zero with PE. The 512-bit register form takes {sae}, a half can be broadcast from memory, and a write mask merges or zeroes words.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, a[i] = h[i] from a _Float16 array to an int16_t array becomes VCVTTPH2W in GCC 14 and Clang 23. GCC converts 32 halves from memory into a ZMM register per pass; Clang builds YMM inputs from 64-bit loads with VINSERTF128, converts them, and gathers the useful words with VPERMT2Q. With -fno-math-errno, (int16_t)rintf(h[i]) adds VRNDSCALEPH before it in Clang. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTTPH2W.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = src2.f16[i]
        zmm1.w[i] = cvtt_int(a, 16)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPH2W, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTSH2SD
• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH

All 686 AVX10.1 instructions