VCVTTPS2DQ

VCVTTPS2DQ converts singles to signed doublewords, rounding toward zero: the VEX and EVEX form of CVTTPS2DQ, whose page explains the truncation, the integer indefinite 80000000h for NaNs and out-of-range values, and how compilers build the unsigned conversion. VEX gives it 128 and 256 bits with AVX; EVEX adds 512 bits, write masks with zeroing, a broadcast single from memory and {sae}, with AVX-512F (now AVX10.1).

MXCSR’s rounding field plays no part#

The T in the name fixes the rounding, so MXCSR.RC is ignored, and the assembly syntax of the EVEX form offers only {sae}, not the embedded rounding modes. In a case recorded on Zen 5 with RC set to round up, 0.5 still gave 0 and 1.5 gave 1, and only the precision flag was set.

What {sae} changes#

With {sae}, on the register-to-register 512-bit form, the conversion raises no exception and sets no flag: an out-of-range input still gives 80000000h, but nothing records that it happened. Zen 5 converted 2^32, 2^63 and -2^63 to 80000000h under {sae} with the invalid exception unmasked (MXCSR 1E40h), took no #XM, and left MXCSR as it was; -2^31, which fits, gave 80000000h too, and 2,147,483,520 gave 7FFFFF80h. Without {sae}, the same out-of-range input sets IE, or faults when IE is unmasked. Code that needs to know about invalid inputs must therefore check them itself, for example by looking again at the inputs of the elements that came out as 80000000h.

Compilers#

For out[i] = (int)in[i] over 1,024 floats, GCC 14 at -O2 with -march=x86-64-v4 converts ZMM registers, while Clang 23 uses YMM registers; with -march=znver5 both use ZMM. _mm512_cvtt_roundps_epi32(x, _MM_FROUND_NO_EXC) gives the {sae} form, and the masked intrinsics the forms with {k}. A loop that converts only the elements selected by a condition becomes, in both compilers, a masked load, an unmasked conversion and a masked store.

Related conversions: VCVTTPS2UDQ to unsigned doublewords, VCVTTPS2QQ to quadwords, and AVX10.2’s VCVTTPS2DQS, which saturates instead of giving the indefinite value. AMD’s Zen 5 guide lists VCVTTPS2DQ as one macro-op with a latency of three cycles at every width.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = src2.f32[i]
        zmm1.d[i] = cvtt_int(a, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPS2DQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD

All 253 AVX instructions

More AVX10.1 instructions

• VCVTSH2SI
• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH

All 686 AVX10.1 instructions