VCVTTPS2DQS instruction (AVX10.2)

VCVTTPS2DQ truncates single-precision values to 32-bit integers, and any value it cannot represent, NaN included, becomes 80000000H, the “integer indefinite” value. That is the most negative integer, so a large positive input produces a large negative result.

VCVTTPS2DQS truncates the same way but saturates: values above the range give 7FFFFFFFH, values below it 80000000H, and NaN gives 0 (when the invalid exception is masked, as it normally is). This is what Rust’s as casts and WebAssembly’s trunc_sat instructions define, so they no longer need a fix-up sequence around the conversion.

The other conversions of the group follow the same rule: VCVTTPS2UDQS, VCVTTPS2QQS, VCVTTPS2UQQS, VCVTTPD2DQS, VCVTTPD2UDQS, VCVTTPD2QQS, VCVTTPD2UQQS and the scalar versions such as VCVTTSS2SIS.

Forms

Every encoding of VCVTTPS2DQS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VCVTTPS2DQS xmm {k}{z}, xmm` VCVTTPS2DQS_XMMi32_MASKmskw_XMMf32_AVX512	`EVEX.128.NP.MAP5.W0 6D /r`	AVX10.2
`VCVTTPS2DQS xmm {k}{z}, m128/m32bcst` VCVTTPS2DQS_XMMi32_MASKmskw_MEMf32_AVX512	`EVEX.128.NP.MAP5.W0 6D /r`	AVX10.2
`VCVTTPS2DQS ymm {k}{z}, ymm` VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512	`EVEX.256.NP.MAP5.W0 6D /r`	AVX10.2
`VCVTTPS2DQS ymm {k}{z}, m256/m32bcst` VCVTTPS2DQS_YMMi32_MASKmskw_MEMf32_AVX512	`EVEX.256.NP.MAP5.W0 6D /r`	AVX10.2
`VCVTTPS2DQS zmm {k}{z}, zmm, {sae}` VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512	`EVEX.512.NP.MAP5.W0 6D /r`	AVX10.2
`VCVTTPS2DQS zmm {k}{z}, m512/m32bcst` VCVTTPS2DQS_ZMMi32_MASKmskw_MEMf32_AVX512	`EVEX.512.NP.MAP5.W0 6D /r`	AVX10.2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Every single works alike: 4, 8 and 16 singles in the xmm, ymm and zmm forms. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m32bcst, one single from memory stands for every element of the last source.

Result single i comes from single i of xmm2. Result singles 3 to 0: r3, unchanged (bit 2 of k1 is 0), r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = src2.f32[i]
        zmm1.d[i] = cvtts_int(a, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Not run on a processor: none of these processors has AVX10.2.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VCVTTPS2DQS xmm {k}{z}, xmm/m128/m32bcst` `VCVTTPS2DQS ymm {k}{z}, ymm/m256/m32bcst` `VCVTTPS2DQS zmm {k}{z}, zmm/m512/m32bcst, {sae}`
`xmm, ymm, zmm`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcst`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms: write masking; follows MXCSR
Memory forms: embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPS2DQS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtts_ps_epi32` `__m128i _mm_cvtts_ps_epi32(__m128 __A)`	`VCVTTPS2DQS xmm, xmm` EVEX.128 -mavx10.2
`_mm_mask_cvtts_ps_epi32` `__m128i _mm_mask_cvtts_ps_epi32(__m128i __W, __mmask8 __U, __m128 __A)`	`VCVTTPS2DQS xmm {k}, xmm` EVEX.128 -mavx10.2
`_mm_maskz_cvtts_ps_epi32` `__m128i _mm_maskz_cvtts_ps_epi32(__mmask8 __U, __m128 __A)`	`VCVTTPS2DQS xmm {k}{z}, xmm` EVEX.128 -mavx10.2
`_mm256_cvtts_ps_epi32` `__m256i _mm256_cvtts_ps_epi32(__m256 __A)`	`VCVTTPS2DQS ymm, ymm` EVEX.256 -mavx10.2
`_mm256_mask_cvtts_ps_epi32` `__m256i _mm256_mask_cvtts_ps_epi32(__m256i __W, __mmask8 __U, __m256 __A)`	`VCVTTPS2DQS ymm {k}, ymm` EVEX.256 -mavx10.2
`_mm256_maskz_cvtts_ps_epi32` `__m256i _mm256_maskz_cvtts_ps_epi32(__mmask8 __U, __m256 __A)`	`VCVTTPS2DQS ymm {k}{z}, ymm` EVEX.256 -mavx10.2
`_mm512_cvtts_ps_epi32` `__m512i _mm512_cvtts_ps_epi32(__m512 __A)`	`VCVTTPS2DQS zmm, zmm` EVEX.512 -mavx10.2
`_mm512_cvtts_roundps_epi32` `__m512i _mm512_cvtts_roundps_epi32(__m512 __A, const int __R)`	`VCVTTPS2DQS zmm, zmm, {sae}` EVEX.512 -mavx10.2
`_mm512_mask_cvtts_ps_epi32` `__m512i _mm512_mask_cvtts_ps_epi32(__m512i __W, __mmask16 __U, __m512 __A)`	`VCVTTPS2DQS zmm {k}, zmm` EVEX.512 -mavx10.2
`_mm512_mask_cvtts_roundps_epi32` `__m512i _mm512_mask_cvtts_roundps_epi32(__m512i __W, __mmask16 __U, __m512 __A, const int __R)`	`VCVTTPS2DQS zmm {k}, zmm, {sae}` EVEX.512 -mavx10.2
`_mm512_maskz_cvtts_ps_epi32` `__m512i _mm512_maskz_cvtts_ps_epi32(__mmask16 __U, __m512 __A)`	`VCVTTPS2DQS zmm {k}{z}, zmm` EVEX.512 -mavx10.2
`_mm512_maskz_cvtts_roundps_epi32` `__m512i _mm512_maskz_cvtts_roundps_epi32(__mmask16 __U, __m512 __A, const int __R)`	`VCVTTPS2DQS zmm {k}{z}, zmm, {sae}` EVEX.512 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX512_SAT_CVT_DS_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_SAT_CVT_DS_256` AVX10.2	Same as `AVX512_SAT_CVT_DS_128`	Same as `AVX512_SAT_CVT_DS_128`
`AVX512_SAT_CVT_DS_512` AVX10.2	Same as `AVX512_SAT_CVT_DS_128`	Same as `AVX512_SAT_CVT_DS_128`

More AVX10.2 instructions

All 96 AVX10.2 instructions