x86-64.net

Instruction

VCVTTPS2DQS

Converts packed singles to 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

VCVTTPS2DQ truncates single-precision values to 32-bit integers, and any value it cannot represent, NaN included, becomes 80000000H, the “integer indefinite” value. That is the most negative integer, so a large positive input produces a large negative result.

VCVTTPS2DQS truncates the same way but saturates: values above the range give 7FFFFFFFH, values below it 80000000H, and NaN gives 0 (when the invalid exception is masked, as it normally is). This is what Rust’s as casts and WebAssembly’s trunc_sat instructions define, so they no longer need a fix-up sequence around the conversion.

The other conversions of the group follow the same rule: VCVTTPS2UDQS, VCVTTPS2QQS, VCVTTPS2UQQS, VCVTTPD2DQS, VCVTTPD2UDQS, VCVTTPD2QQS, VCVTTPD2UQQS and the scalar versions such as VCVTTSS2SIS.

Forms

Every encoding of VCVTTPS2DQS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTTPS2DQS xmm {k}{z}, xmm VCVTTPS2DQS_XMMi32_MASKmskw_XMMf32_AVX512EVEX.128.NP.MAP5.W0 6D /rAVX10.2
VCVTTPS2DQS xmm {k}{z}, m128/m32bcst VCVTTPS2DQS_XMMi32_MASKmskw_MEMf32_AVX512EVEX.128.NP.MAP5.W0 6D /rAVX10.2
VCVTTPS2DQS ymm {k}{z}, ymm VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512EVEX.256.NP.MAP5.W0 6D /rAVX10.2
VCVTTPS2DQS ymm {k}{z}, m256/m32bcst VCVTTPS2DQS_YMMi32_MASKmskw_MEMf32_AVX512EVEX.256.NP.MAP5.W0 6D /rAVX10.2
VCVTTPS2DQS zmm {k}{z}, zmm, {sae} VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512EVEX.512.NP.MAP5.W0 6D /rAVX10.2
VCVTTPS2DQS zmm {k}{z}, m512/m32bcst VCVTTPS2DQS_ZMMi32_MASKmskw_MEMf32_AVX512EVEX.512.NP.MAP5.W0 6D /rAVX10.2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPS2DQS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtts_ps_epi32 __m128i _mm_cvtts_ps_epi32(__m128 __A)

VCVTTPS2DQS xmm, xmm EVEX.128 -mavx10.2

_mm_mask_cvtts_ps_epi32 __m128i _mm_mask_cvtts_ps_epi32(__m128i __W, __mmask8 __U, __m128 __A)

VCVTTPS2DQS xmm {k}, xmm EVEX.128 -mavx10.2

_mm_maskz_cvtts_ps_epi32 __m128i _mm_maskz_cvtts_ps_epi32(__mmask8 __U, __m128 __A)

VCVTTPS2DQS xmm {k}{z}, xmm EVEX.128 -mavx10.2

_mm256_cvtts_ps_epi32 __m256i _mm256_cvtts_ps_epi32(__m256 __A)

VCVTTPS2DQS ymm, ymm EVEX.256 -mavx10.2

_mm256_mask_cvtts_ps_epi32 __m256i _mm256_mask_cvtts_ps_epi32(__m256i __W, __mmask8 __U, __m256 __A)

VCVTTPS2DQS ymm {k}, ymm EVEX.256 -mavx10.2

_mm256_maskz_cvtts_ps_epi32 __m256i _mm256_maskz_cvtts_ps_epi32(__mmask8 __U, __m256 __A)

VCVTTPS2DQS ymm {k}{z}, ymm EVEX.256 -mavx10.2

_mm512_cvtts_ps_epi32 __m512i _mm512_cvtts_ps_epi32(__m512 __A)

VCVTTPS2DQS zmm, zmm EVEX.512 -mavx10.2

_mm512_cvtts_roundps_epi32 __m512i _mm512_cvtts_roundps_epi32(__m512 __A, const int __R)

VCVTTPS2DQS zmm, zmm, {sae} EVEX.512 -mavx10.2

_mm512_mask_cvtts_ps_epi32 __m512i _mm512_mask_cvtts_ps_epi32(__m512i __W, __mmask16 __U, __m512 __A)

VCVTTPS2DQS zmm {k}, zmm EVEX.512 -mavx10.2

_mm512_mask_cvtts_roundps_epi32 __m512i _mm512_mask_cvtts_roundps_epi32(__m512i __W, __mmask16 __U, __m512 __A, const int __R)

VCVTTPS2DQS zmm {k}, zmm, {sae} EVEX.512 -mavx10.2

_mm512_maskz_cvtts_ps_epi32 __m512i _mm512_maskz_cvtts_ps_epi32(__mmask16 __U, __m512 __A)

VCVTTPS2DQS zmm {k}{z}, zmm EVEX.512 -mavx10.2

_mm512_maskz_cvtts_roundps_epi32 __m512i _mm512_maskz_cvtts_roundps_epi32(__mmask16 __U, __m512 __A, const int __R)

VCVTTPS2DQS zmm {k}{z}, zmm, {sae} EVEX.512 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_SAT_CVT_DS_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_SAT_CVT_DS_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_SAT_CVT_DS_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.