VCVTTPS2IBS

VCVTTPS2IBS converts each single to a signed byte, truncating toward zero, and saturates: 128 or more gives 7Fh, -129 or less gives 80h, and a NaN gives 0. It is VCVTPS2IBS with the rounding fixed, opcode 68h for 69h; that page covers the in-place layout, each byte in the low byte of its doubleword, and the rest of the family. Truncation moves the edges of the range: 127.9 gives 127 and -128.9 gives -128, each with PE alone, while 128 and -129 set IE, as do infinities and NaNs. The 512-bit register form takes {sae} instead of {er}, which keeps those from being reported but leaves the results.

The result is what C gives for a single first clamped to -128 and 127 and then converted to int8_t, apart from NaNs, for which C defines no result. VCVTTPS2DQ truncates the same way to doublewords and returns 80000000h for anything out of range; VCVTTPS2DQS is the saturating doubleword form.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles _mm512_ipcvtts_ps_epi8 to vcvttps2ibs zmm0, zmm0 and _mm512_ipcvtts_roundps_epi8(x, _MM_FROUND_NO_EXC) to vcvttps2ibs zmm0, zmm0, {sae}. The clamp loop above, written in C, keeps VMAXPS, VMINPS, VCVTTPS2DQ and VPMOVDB. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = src2.f32[i]
        zmm1.d[i] = cvtts_int(a, 8) & 0xFF
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPS2IBS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16

All 96 AVX10.2 instructions