VCVTTPS2QQ

VCVTTPS2QQ converts singles to signed quadwords, truncating toward zero whatever MXCSR.RC says: the vector form of C’s cast from float to int64_t. Each result is twice as wide as its source, so 2 singles from the low half of an XMM register or from memory fill an XMM register, 4 a YMM register and 8 a ZMM one. It came with AVX512DQ, as the truncating form of VCVTPS2QQ and the single-source form of VCVTTPD2QQ, whose page covers the range. A single of magnitude 2^23 or more is already an integer, so every single from -2^63 up to below 2^63 converts; a NaN, an infinity or anything larger gives the integer indefinite, 8000000000000000h, and sets IE. VCVTTPS2UQQ converts to unsigned quadwords.

Recorded on Zen 5#

• Past 32 bits. {evex} vcvttps2qq xmm17, xmm30 turned 2^31 into 80000000h and -2^31 into FFFFFFFF80000000h, without a flag, and a broadcast 2^32 gave 100000000h: all three overflow the doubleword result of VCVTTPS2DQ.
• Toward zero. With MXCSR rounding down, -0.5, 1.5 and -2.5 gave 0, 1 and -2, and set PE.
• With {sae}. In vcvttps2qq zmm14{k5}, ymm8, {sae}, with IE unmasked, the largest finite single gave 8000000000000000h, 4.0 gave 4 and 0.5 and -0.5 gave 0, without a fault or a flag.

In compiled code#

At -O2 with -march=x86-64-v4, both compilers vectorize s[i] = (int64_t)f[i] over a float and an int64_t array with VCVTTPS2QQ: GCC 14 loads 16 singles into a ZMM register and converts each half into a ZMM register, taking the upper half out with VEXTRACTF32X8, while Clang 23 converts 4 singles at a time from memory into YMM registers. A single cast is VCVTTSS2SI. _mm512_cvttps_epi64 is one VCVTTPS2QQ.

AMD’s Zen 5 latency spreadsheet gives the same rows as for VCVTPS2QQ: one macro-op on pipe FP2 or FP3 and 3 cycles for the XMM form and the YMM form from memory, two macro-ops and 4 cycles for the YMM form from a register, and two macro-ops and 6 cycles for the ZMM form.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f32[i]
        zmm1.q[i] = cvtt_int(a, 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Half); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPS2QQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTSH2SS
• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW

All 686 AVX10.1 instructions