x86-64.net

Instruction

VCVTTPS2QQ

Converts packed singles to signed quadwords, truncating toward zero.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTTPS2QQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTTPS2QQ xmm {k}{z}, xmm VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512EVEX.128.66.0F.W0 7A /rAVX10.1 or AVX512DQ + AVX512VL
VCVTTPS2QQ xmm {k}{z}, m128/m32bcst VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512EVEX.128.66.0F.W0 7A /rAVX10.1 or AVX512DQ + AVX512VL
VCVTTPS2QQ ymm {k}{z}, xmm VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512EVEX.256.66.0F.W0 7A /rAVX10.1 or AVX512DQ + AVX512VL
VCVTTPS2QQ ymm {k}{z}, m256/m32bcst VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512EVEX.256.66.0F.W0 7A /rAVX10.1 or AVX512DQ + AVX512VL
VCVTTPS2QQ zmm {k}{z}, ymm, {sae} VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512EVEX.512.66.0F.W0 7A /rAVX10.1 or AVX512DQ
VCVTTPS2QQ zmm {k}{z}, m512/m32bcst VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512EVEX.512.66.0F.W0 7A /rAVX10.1 or AVX512DQ

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPS2QQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvttps_epi64 __m128i _mm_cvttps_epi64(__m128 __A)

VCVTTPS2QQ xmm, xmm EVEX.128 -mavx512vl -mavx512dq

_mm_mask_cvttps_epi64 __m128i _mm_mask_cvttps_epi64(__m128i __W, __mmask8 __U, __m128 __A)

VCVTTPS2QQ xmm {k}, xmm EVEX.128 -mavx512vl -mavx512dq

_mm_maskz_cvttps_epi64 __m128i _mm_maskz_cvttps_epi64(__mmask8 __U, __m128 __A)

VCVTTPS2QQ xmm {k}{z}, xmm EVEX.128 -mavx512vl -mavx512dq

_mm256_cvttps_epi64 __m256i _mm256_cvttps_epi64(__m128 __A)

VCVTTPS2QQ ymm, xmm EVEX.256 -mavx512vl -mavx512dq

_mm256_mask_cvttps_epi64 __m256i _mm256_mask_cvttps_epi64(__m256i __W, __mmask8 __U, __m128 __A)

VCVTTPS2QQ ymm {k}, xmm EVEX.256 -mavx512vl -mavx512dq

_mm256_maskz_cvttps_epi64 __m256i _mm256_maskz_cvttps_epi64(__mmask8 __U, __m128 __A)

VCVTTPS2QQ ymm {k}{z}, xmm EVEX.256 -mavx512vl -mavx512dq

_mm512_cvtt_roundps_epi64 __m512i _mm512_cvtt_roundps_epi64(__m256 A, const int R)

VCVTTPS2QQ zmm, ymm, {sae} EVEX.512 -mavx512dq

_mm512_cvttps_epi64 __m512i _mm512_cvttps_epi64(__m256 __A)

VCVTTPS2QQ zmm, ymm EVEX.512 -mavx512dq

_mm512_mask_cvtt_roundps_epi64 __m512i _mm512_mask_cvtt_roundps_epi64(__m512i W, __mmask8 U, __m256 A, const int R)

VCVTTPS2QQ zmm {k}, ymm, {sae} EVEX.512 -mavx512dq

_mm512_mask_cvttps_epi64 __m512i _mm512_mask_cvttps_epi64(__m512i __W, __mmask8 __U, __m256 __A)

VCVTTPS2QQ zmm {k}, ymm EVEX.512 -mavx512dq

_mm512_maskz_cvtt_roundps_epi64 __m512i _mm512_maskz_cvtt_roundps_epi64(__mmask8 U, __m256 A, const int R)

VCVTTPS2QQ zmm {k}{z}, ymm, {sae} EVEX.512 -mavx512dq

_mm512_maskz_cvttps_epi64 __m512i _mm512_maskz_cvttps_epi64(__mmask8 __U, __m256 __A)

VCVTTPS2QQ zmm {k}{z}, ymm EVEX.512 -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512DQ_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512DQ_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512DQ_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.