VCVTTPS2QQS

VCVTTPS2QQS converts singles to signed quadwords, truncating toward zero, and saturates where VCVTTPS2QQ gives the indefinite 8000000000000000h: 2^63 or more becomes 7FFFFFFFFFFFFFFFh, less than -2^63 becomes 8000000000000000h, and a NaN becomes 0. The result is twice as wide as the source, so two, four or eight singles come from the low half of the source register or from 8, 16 or 32 bytes of memory. It belongs to AVX10.2: opcode 6Dh in EVEX map 5 with a 66 prefix and W0, with a write mask, a broadcast single and {sae} on the 512-bit form. NaNs, infinities and out-of-range values still set IE, and a lost fraction sets PE. VCVTTPS2DQS’s page covers why saturation matters.

Bounds from the wrong width#

The AVX10.2 specification’s helper for this conversion (revision 7.0) sets its out-of-range test with 64-bit bounds but saturates with the doubleword bounds 2^31 - 1 and -2^31, so taken literally it would clamp every single beyond about two billion, though the quadword holds it. The description, which returns any representable truncated value, is the intended rule. VCVTTPD2QQS’s helper has a slip of its own.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles _mm512_cvtts_ps_epi64 to vcvttps2qqs zmm0, ymm0, while a loop converting floats to int64_t keeps VCVTTPS2QQ. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f32[i]
        zmm1.q[i] = cvtts_int(a, 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Half); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPS2QQS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16

All 96 AVX10.2 instructions