VCVTTPS2UDQ

VCVTTPS2UDQ truncates singles toward zero to unsigned doublewords, 4, 8 or 16 at a time: the vector form of C’s conversion from float to uint32_t. It is the unsigned partner of VCVTTPS2DQ, whose page covers truncation and the integer indefinite; here the valid range is 0 to 2^32 - 1, and the indefinite is FFFFFFFFh, the largest unsigned value, rather than 80000000h. It came with AVX512F, and as an EVEX instruction it takes a write mask, a 32-bit broadcast and, in the 512-bit register form, {sae}.

Recorded on Zen 5#

• Negative input. -1.0 gave FFFFFFFFh, as did -2^63 from a broadcast, -2^32, the largest negative single and negative infinity: anything at or below -1 is out of range, while a negative denormal gave 0.
• Large input. 2^32, 2^63, about 10^30 and the largest single gave FFFFFFFFh and set IE; signaling NaNs did the same.
• Flags of masked elements. With three denormals and the smallest normal masked off by zeroing, vcvttps2udq ymm17{k5}{z}, ymm30 set only IE, for its out-of-range elements, and no PE: elements left out raise nothing.
• {sae}. With IE unmasked in MXCSR, the 512-bit form gave FFFFFFFFh for -1.0 and negative infinity without a fault or a flag.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile u[i] = (uint32_t)f[i] to VCVTTPS2UDQ from memory, GCC on ZMM registers and Clang on YMM registers, unrolled four times. With -march=x86-64-v3 both build it from VCVTTPS2DQ: values from 2^31 up are reduced by 2^31 with VSUBPS before a second conversion, and the two results are merged, GCC with a compare and VPXOR of the shifted sign bit, Clang with VPSRAD, VPAND and VPOR. _mm512_cvttps_epu32 is one VCVTTPS2UDQ.

AMD’s Zen 5 latency spreadsheet gives every width one macro-op on pipe FP2 or FP3 and 3 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = src2.f32[i]
        zmm1.d[i] = cvtt_uint(a, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPS2UDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTSH2USI
• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD

All 686 AVX10.1 instructions