VCVTTPS2UDQS

VCVTTPS2UDQS converts singles to unsigned doublewords, truncating toward zero, and saturates: 2^32 or more becomes FFFFFFFFh, -1 or less becomes 0, and a NaN becomes 0. VCVTTPS2UDQ returns FFFFFFFFh, the unsigned indefinite, for all of those, so there a negative input reads as the largest value. Inputs between -1 and 0 truncate to 0 in both, without the invalid exception. Source and result have the same width, 4, 8 or 16 elements. It belongs to AVX10.2: opcode 6Ch in EVEX map 5, no prefix, W0, one below the signed VCVTTPS2DQS’s 6Dh, with a write mask, a broadcast single and {sae} on the 512-bit form. NaNs, infinities and out-of-range values still set IE, and a lost fraction sets PE.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles _mm512_cvtts_ps_epu32 to vcvttps2udqs zmm0, zmm0; a loop converting floats to uint32_t keeps VCVTTPS2UDQ. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = src2.f32[i]
        zmm1.d[i] = cvtts_uint(a, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPS2UDQS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16

All 96 AVX10.2 instructions