VCVTTPS2UQQ

VCVTTPS2UQQ converts singles to unsigned quadwords, 2, 4 or 8 at a time into an XMM, YMM or ZMM register, truncating toward zero whatever MXCSR.RC says: the vector form of C’s cast from float to uint64_t. It is the unsigned partner of VCVTTPS2QQ, which came with it in AVX512DQ, the truncating form of VCVTPS2UQQ and the quadword form of VCVTTPS2UDQ. A value that truncates to 0 to 2^64 - 1 converts, so -0.5 gives 0; a negative value of -1 or less, a NaN, an infinity or a value of 2^64 or more gives FFFFFFFFFFFFFFFFh and sets IE.

Recorded on Zen 5#

• Negative values. A broadcast -1.5 gave FFFFFFFFFFFFFFFFh in both elements of vcvttps2uqq xmm7{k7}{z}, dword bcst [...] and set IE, as did -2^31.
• Large singles. 4EFFFFFFh, the largest single below 2^31, gave 7FFFFF80h, from a register and from memory.
• DAZ. With DAZ set, the smallest and the largest denormal both gave 0, without PE: the inputs count as zeros, which convert exactly.
• With {sae}. In vcvttps2uqq zmm14{k4}, ymm8, {sae}, with IE unmasked, -1.0 and -2.5 gave FFFFFFFFFFFFFFFFh, while 4.0, 1.5 and 2.5 gave 4, 1 and 2, without a fault or a flag.

In compiled code#

At -O2 with -march=x86-64-v4, both compilers vectorize u[i] = (uint64_t)f[i] with VCVTTPS2UQQ, GCC 14 on ZMM registers and Clang 23 on YMM registers, 4 singles at a time from memory, as for the signed cast. A single cast is VCVTTSS2USI. _mm512_cvttps_epu64 is one VCVTTPS2UQQ.

AMD’s Zen 5 latency spreadsheet gives the same rows as for VCVTTPS2QQ: 3 cycles for the XMM form, 4 for the YMM form from a register and 6 for the ZMM form, with one macro-op from memory at YMM width.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f32[i]
        zmm1.q[i] = cvtt_uint(a, 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Half); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTPS2UQQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTSI2SD
• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH

All 686 AVX10.1 instructions